公开(公告)号：US20080157343A1

公开(公告)日：2008-07-03

申请号：US11648220

申请日：2006-12-29

Applicant: Sriram Dattaguru ,  Larry Binder ,  Cengiz A. Palanduz ,  Chris Jones ,  Dave Bach ,  Kaladhar Radhakrishnan ,  Timothe Litt

Inventor： Sriram Dattaguru ,  Larry Binder ,  Cengiz A. Palanduz ,  Chris Jones ,  Dave Bach ,  Kaladhar Radhakrishnan ,  Timothe Litt

IPC: H01L23/13

CPC classification number: H05K1/0262 ,  H01L23/642 ,  H01L25/162 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/19106 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/0401

Abstract: In some embodiments, a ceramic interposer with silicon voltage regulator and array capacitor combination for integrated circuit packages is presented. In this regard, an apparatus is introduced having a bowl-shaped ceramic interposer containing conductive traces, one or more silicon voltage regulator(s) coupled with contacts on a first surface of the ceramic interposer, and one or more array capacitor(s) coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，提供了具有用于集成电路封装的硅电压调节器和阵列电容器组合的陶瓷插入器。 在这方面，引入了一种装置，其具有包含导电迹线的碗形陶瓷插入器，与陶瓷插入件的第一表面上的触点耦合的一个或多个硅电压调节器，以及一个或多个耦合的阵列电容器 在陶瓷插入件的第二表面上具有触点。 还公开并要求保护其他实施例。

公开(公告)号：US20080151516A1

公开(公告)日：2008-06-26

申请号：US11959232

申请日：2007-12-18

Applicant: Daigo Suzuki ,  Minoru Takizawa ,  Nobuhiro Yamamoto ,  Hidenori Tanaka

Inventor： Daigo Suzuki ,  Minoru Takizawa ,  Nobuhiro Yamamoto ,  Hidenori Tanaka

IPC: H05K1/18 ,  H05K3/36 ,  H05K1/02

CPC classification number: H05K1/186 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19043 ,  H05K1/113 ,  H05K3/4611 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/2036 ,  Y10T29/49126 ,  H01L2224/05599

Abstract: According to one embodiment, there is provided a printed-wiring board, includes a first base member including a component mounting face, a first electronic component with a through-electrode mounted on the component mounting face, a second base member stacked on the first base member via an insulating layer covering the first electronic component, a hole part provided in the second base member and communicating with the through-electrode of the first electronic component, and a second electronic component mounted on the second base member and circuit-connected directly to the through-electrode via the hole part.

Abstract translation: 根据一个实施例，提供了一种印刷电路板，包括：第一基座构件，包括部件安装面;第一电子部件，其具有安装在部件安装面上的通孔;第二基座部件，堆叠在第一基座 构件，其经由覆盖所述第一电子部件的绝缘层，设置在所述第二基座构件中并与所述第一电子部件的通孔连通的孔部，以及安装在所述第二基座构件上的电路部件， 通孔通过孔部分。

公开(公告)号：US20080142940A1

公开(公告)日：2008-06-19

申请号：US11612041

申请日：2006-12-18

Applicant: Rajiv Carl Dunne

Inventor： Rajiv Carl Dunne

IPC: H01L21/00 ,  H01L25/04

CPC classification number: H01L23/5389 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H05K1/186 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/10515 ,  H05K2203/063 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor system having a substrate (101) including a rigid insulating interposer (110) with a high modulus and a top (140) and a bottom (150) low-modulus tape with flip-attached semiconductor chips (120, 130). The assembled chips, with the passive surfaces facing each other, are located in an opening (114) of the interposer, which has a thickness (111) equal to or smaller than the sum of the assembled two chips. Adhesive material (160) holds the tapes parallel to the interposer and the chip surfaces together. Solder balls (180) and discrete components (170) may be attached to the outside surfaces of the tapes.

Abstract translation: 一种具有衬底（101）的半导体系统，包括具有高模量的刚性绝缘插入件（110）和具有翻转连接的半导体芯片（120,130）的顶部（140）和底部（150）低模量带。 具有被动表面彼此相对的组装芯片位于插入件的开口（114）中，其具有等于或小于组装的两个芯片的总和的厚度（111）。 粘合材料（160）将带平行于插入件并将芯片表面保持在一起。 焊球（180）和分立部件（170）可以附接到带的外表面。

公开(公告)号：US07375429B2

公开(公告)日：2008-05-20

申请号：US11321811

申请日：2005-12-29

Applicant: Yasuhiro Teshima ,  Noboru Nakama

Inventor： Yasuhiro Teshima ,  Noboru Nakama

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H05K1/0231 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/66 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/17104 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/023 ,  H05K1/025 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/10022 ,  H05K2201/10515 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00012

Abstract: Disclosed are an integrated circuit component capable of simply mounting at low cost a chip part which adjusts impedance of wiring patterns as well as capable of effectively reducing switching noise from an integrated circuit, and a method for mounting the chip part. The integrated circuit component of the present invention has a constitution that a bypass capacitor is mounted on a wiring board side of a gap between the wiring board and an LSI chip. Therefore, as compared with a case where the capacitor is mounted on the LSI chip side, a transmission path through the capacitor can be extremely shortened. As a result, inductance components of the feeder line can be reduced, so that a response delay of power transmitted through the feeder line can be sufficiently suppressed.

Abstract translation: 公开了能够以低成本简单地安装芯片部分的集成电路部件，其调整布线图案的阻抗以及能够有效地降低集成电路的开关噪声，以及用于安装芯片部分的方法。 本发明的集成电路部件具有在布线基板和LSI芯片之间的间隙的布线基板侧安装旁路电容器的结构。 因此，与将电容器安装在LSI芯片侧的情况相比，可以极大地缩短通过电容器的传输路径。 结果，可以减少馈电线路的电感分量，从而可以充分抑制通过馈电线路传输的功率的响应延迟。

公开(公告)号：US07375418B2

公开(公告)日：2008-05-20

申请号：US11452532

申请日：2006-06-14

Applicant: Julian Partridge

Inventor： Julian Partridge

IPC: H01L23/02

CPC classification number: H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/141 ,  H05K2201/049 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element while traces that implement stacking-related intra-stack connections between the constituent ICs are implemented in interposers or carrier structures oriented along the leaded sides of the stack and which extend beyond the perimeter of the feet of the leads of the constituent ICs or beyond the connective pads of the interposer. This leaves open to air flow, most of the transit section of the lower lead for cooling, but provides a less complex board structure for implementation of intra-stack connections.

Abstract translation: 本发明提供了一种系统和方法，用于选择性地堆叠和互连带有封装的集成电路器件，其上部IC元件的引线的脚与下部IC元件的引线的上部肩部之间的连接， 组成IC之间的堆叠连接在沿着堆叠的引导侧定向的插入件或载体结构中实现，并且延伸超过构成IC的引线的脚的周边或超过插入器的连接焊盘。 这使得空气流动，下部引线的大部分转接段用于冷却，但是提供了一种不太复杂的板结构，用于实现堆叠内连接。

公开(公告)号：US20080036059A1

公开(公告)日：2008-02-14

申请号：US11463799

申请日：2006-08-10

Applicant: Jens Pohl ,  Michael Bauer

Inventor： Jens Pohl ,  Michael Bauer

IPC: H01L25/10 ,  B65B35/50 ,  H01L23/40 ,  H01L23/488

CPC classification number: H05K3/303 ,  H01L23/49816 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/0212 ,  H05K2201/10515 ,  H05K2203/048 ,  H05K2203/083 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The invention relates to a method in which components (101, 102) are provided, movement elements (104) are in each case applied to surfaces of a number of the components (101), and the components (101, 102) are stacked, so that one or a plurality of the movement elements (104) are situated between adjacent components (101, 102) and the components (101, 102) are held in their position by connecting elements (103).

Abstract translation: 本发明涉及一种其中提供部件（101,102）的方法，每种情况下运动元件（104）施加到多个部件（101）的表面，并且部件（101,102）被堆叠， 使得一个或多个运动元件（104）位于相邻部件（101,102）之间，并且部件（101,102）通过连接元件（103）保持在其位置。

公开(公告)号：US20080023814A1

公开(公告)日：2008-01-31

申请号：US11829851

申请日：2007-07-27

Applicant: Seung-Yeol YANG

Inventor： Seung-Yeol YANG

IPC: H01L23/488

CPC classification number: H01L25/105 ,  H01L23/49805 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/8385 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K3/3442 ,  H05K3/368 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09845 ,  H05K2201/10515 ,  H05K2201/10727 ,  H05K2203/041 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided is a stacked ball grid array (BGA) semiconductor package. The stacked BGA semiconductor package includes: a single semiconductor package having landings provided in depressed grooves of both sides thereof, wherein the landings include a conductive material, and a substrate having a semiconductor chip disposed on the substrate; another semiconductor package formed above the single semiconductor package and having landing pads formed in a lower surface of the substrate thereof; and solder balls connecting the landing pads to the landings.

Abstract translation: 提供了一种堆叠球栅阵列（BGA）半导体封装。 堆叠的BGA半导体封装包括：单个半导体封装，其具有设置在其两侧的凹槽中的着陆，其中所述着陆包括导电材料，以及具有设置在所述衬底上的半导体芯片的衬底; 形成在单个半导体封装之上并具有形成在其基板的下表面中的着​​陆焊盘的另一半导体封装; 以及将着陆垫连接到平台上的焊球。

公开(公告)号：US07316574B2

公开(公告)日：2008-01-08

申请号：US11027992

申请日：2005-01-04

Applicant: Kenny Che ,  Andrew Wu ,  Zi Fu Zheng

Inventor： Kenny Che ,  Andrew Wu ,  Zi Fu Zheng

IPC: H01R12/00

CPC classification number: H05K1/141 ,  H05K3/3447 ,  H05K2201/049 ,  H05K2201/10053 ,  H05K2201/10106 ,  H05K2201/10121 ,  H05K2201/10128 ,  H05K2201/10189 ,  H05K2201/10424 ,  H05K2201/10477 ,  H05K2201/10515

Abstract: An electrical component is mounted on a carrier printed circuit board. A first header connector connects the carrier printed circuit board to a printed circuit board on one side of the electrical component. A second header connector connects the carrier printed circuit board to the printed circuit board on the opposite side of the electrical component. The carrier printed circuit board and the printed circuit board are connected so that the electrical component is sandwiched between the carrier printed circuit board and the printed circuit board. The carrier printed circuit board, the first header connector, and the second header connector protect the electrical component from impact and mechanical stress. The carrier printed circuit board redistributes the electrical connection of the electrical component.

Abstract translation: 电气部件安装在载体印刷电路板上。 第一标头连接器将载体印刷电路板连接到电气部件一侧的印刷电路板。 第二标头连接器将载体印刷电路板连接到电气部件相反侧的印刷电路板。 载体印刷电路板和印刷电路板被连接，使得电气部件夹在载体印刷电路板和印刷电路板之间。 载体印刷电路板，第一插头连接器和第二插头连接器保护电气部件免受冲击和机械应力。 载体印刷电路板重新分布电气部件的电气连接。

公开(公告)号：US20080003712A1

公开(公告)日：2008-01-03

申请号：US11600946

申请日：2006-11-16

Applicant: Walter Moden ,  Jerrold King ,  Jerry Brooks

Inventor： Walter Moden ,  Jerrold King ,  Jerry Brooks

IPC: H01L21/00

CPC classification number: H05K1/181 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/145 ,  H05K1/147 ,  H05K2201/049 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49169 ,  H01L2924/00

Abstract: A method for a low profile multi-IC chip package for high-speed applications comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage or, alternatively, are directly fixed to leads or pads on the host circuit board.

Abstract translation: 用于高速应用的低轮廓多IC芯片封装的方法包括用于电连接一组堆叠的初级半导体封装的等效外引线的连接器。 在一个实施例中，连接器包括两部分柔性绝缘聚合物片，其一端形成有总线。 在另一个实施例中，连接器包括由导电聚合物形成的多个总线。 在另外的实施例中，初级封装堆叠在保持架内并且使它们的外部引线与保持架内的总线不连接地接触，或者替代地直接固定到主电路板上的引线或焊盘上。

公开(公告)号：US20080001307A1

公开(公告)日：2008-01-03

申请号：US11476956

申请日：2006-06-28

Applicant: Michael Neve de Mevergnies ,  Jean-Pierre Seifert

Inventor： Michael Neve de Mevergnies ,  Jean-Pierre Seifert

IPC: H01L23/48

CPC classification number: H05K1/181 ,  H01L23/585 ,  H01L2924/0002 ,  H05K1/0275 ,  H05K2201/09781 ,  H05K2201/10159 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: A method, apparatus, and system, the apparatus including, in some embodiments, a printed circuit board (PCB), an integrated circuit (IC) positioned over and electrically connected to the PCB, a chip positioned between the PCB and the IC, and a closed boundary barrier between and contacting the PCB and the IC to define an inner containment area that completely contains the chip within the inner containment area.

Abstract translation: 一种方法，装置和系统，该装置在一些实施例中包括印刷电路板（PCB），位于PCB上并电连接到PCB的集成电路（IC），位于PCB和IC之间的芯片，以及 在PCB和IC之间形成封闭的边界屏障并且与PCB接触以限定在内部容纳区域内完全包含芯片的内部容纳区域。