公开(公告)号：US09706656B2

公开(公告)日：2017-07-11

申请号：US14950584

申请日：2015-11-24

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chien-Min Hsu ,  Shih-Hsien Wu ,  Jing-Yao Chang ,  Tao-Chih Chang ,  Ren-Shin Cheng ,  Min-Lin Lee

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42

CPC classification number: H05K1/116 ,  H05K1/0251 ,  H05K3/42 ,  H05K2201/0187 ,  H05K2201/09545 ,  H05K2203/1105 ,  H05K2203/1178 ,  H05K2203/143 ,  H05K2203/1438

Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.

公开(公告)号：US20170150592A1

公开(公告)日：2017-05-25

申请号：US15423584

申请日：2017-02-03

Applicant: MPI corporation

Inventor： WEI-CHENG KU ,  JUN-LIANG LAI ,  CHIH-HAO HO

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/111 ,  H05K1/113 ,  H05K1/114 ,  H05K1/18 ,  H05K3/421 ,  H05K3/426 ,  H05K3/429 ,  H05K2201/041 ,  H05K2201/09545 ,  H05K2203/0369 ,  H05K2203/1461

Abstract: A multilayer circuit board includes a first substrate and a second substrate in stack. The first substrate is provided with two first pads, two second pads, and two first sub-circuits. The first pads and the second pads are electrically connected to the first sub-circuits. The second substrate has a top surface, a bottom surface, a lateral edge, and two openings. The bottom surface of the second substrate is attached to the top surface of the first substrate. The openings extend from the top surface to the bottom surface of the second substrate. The first pads of the first substrate are in the opening of the second substrate; the second pads of the first substrate are not covered by the second substrate. The second substrate is further provided with a pad on the top surface and a second sub-circuit electrically connected to the pad of the second substrate.

公开(公告)号：US20170027057A1

公开(公告)日：2017-01-26

申请号：US15216735

申请日：2016-07-22

Applicant: IBIDEN CO., LTD.

Inventor： Masatoshi KUNIEDA ,  Takafumi OKUMURA

IPC: H05K1/11 ,  H01L23/31 ,  H05K1/09 ,  H01L23/00 ,  H05K3/18 ,  H05K3/42

CPC classification number: H05K1/115 ,  H01L23/3114 ,  H01L24/14 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H05K3/185 ,  H05K3/422 ,  H05K3/424 ,  H05K2201/09545 ,  H05K2201/09627 ,  H05K2201/09645 ,  H05K2203/0723

Abstract: A method for manufacturing a printed wiring board includes forming, on a surface of an insulating layer, a patterned catalyst film including a catalyst for electroless plating such that the patterned catalyst film has a pattern corresponding to a conductor circuit, and applying electroless plating on the patterned catalyst film such that a conductor metal is deposited on the patterned catalyst film and that the conductor circuit is formed on the surface of the insulating layer.

Abstract translation: 一种制造印刷电路板的方法包括在绝缘层的表面上形成图案化催化剂膜，该图案化催化剂膜包括用于化学镀的催化剂，使得图案化的催化剂膜具有与导体电路相对应的图案，并且在 图案化的催化剂膜，使得导体金属沉积在图案化的催化剂膜上，并且导体电路形成在绝缘层的表面上。

公开(公告)号：US09491881B2

公开(公告)日：2016-11-08

申请号：US14164403

申请日：2014-01-27

Applicant: Joshua D. Heppner ,  Zhichao Zhang ,  Srikant Nekkanty ,  Michael Garcia

Inventor： Joshua D. Heppner ,  Zhichao Zhang ,  Srikant Nekkanty ,  Michael Garcia

IPC: H05K7/10 ,  H01R12/70 ,  H05K1/18 ,  H05K3/42

CPC classification number: H05K7/1069 ,  H01R12/7076 ,  H01R12/7082 ,  H05K1/184 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/10189 ,  H05K2201/10265 ,  Y10T29/49222

Abstract: A microelectronic socket having a two piece construction, wherein a first piece comprises a conductive socket substrate and the second piece comprises an insulative insert. The conductive socket substrate has a first surface, a second surface, and at least one opening extending therebetween. The insulative insert has a base portion with at least one projection extending therefrom. The insulative insert is mated with the conductive socket substrate such that the at least one projection resides within a corresponding conductive socket substrate opening. The insulative insert further includes a plurality of vias, wherein at least one of the plurality of vias extends through the insulative base and through an insulative insert projection, wherein a contact may be disposed within the via.

Abstract translation: 一种具有两件式结构的微电子插座，其中第一件包括导电插座衬底，第二件包括绝缘插入件。 导电插座基板具有第一表面，第二表面和在它们之间延伸的至少一个开口。 绝缘插入件具有从其延伸的至少一个突起的基部。 绝缘插入件与导电插座基板配合，使得至少一个突起位于相应的导电插座衬底开口内。 绝缘插入件还包括多个通孔，其中多个通孔中的至少一个延伸穿过绝缘基底并穿过绝缘插入物突起，其中触点可以设置在通孔内。

公开(公告)号：US20160278208A1

公开(公告)日：2016-09-22

申请号：US14834205

申请日：2015-08-24

Applicant: Multek Technologies Ltd.

Inventor： Kwan Pen ,  Pui Yin Yu

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/42 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K1/115 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0058 ,  H05K3/06 ,  H05K3/181 ,  H05K3/188 ,  H05K3/42 ,  H05K3/422 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/095 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/10303

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

Abstract translation: 用于制造电路板的选择性段通过电镀工艺选择性地将内部导电层互连在相同的通孔内的单独的段。 将电镀抗蚀剂施加到内芯的导电层，然后在无电镀处理之后剥离。 在电镀抗蚀剂上剥离化学镀导致通孔壁上的电镀不连续。 在随后的电镀工艺中，由于电镀不连续性，插头非导电层不能镀覆。 所得到的电路板结构在通孔内具有单独的电互连段。

公开(公告)号：US20160057866A1

公开(公告)日：2016-02-25

申请号：US14463012

申请日：2014-08-19

Applicant: JSR CORPORATION

Inventor： Sugirou SHIMODA ,  Kenzou Ookita ,  Isao Aritome ,  Kazuto Watanabe ,  Kenrou Tanaka

IPC: H05K3/00 ,  H01L23/48 ,  H01L21/768 ,  H01L27/108 ,  H01L23/532 ,  C08K5/17 ,  H05K1/09 ,  H05K1/02 ,  C09D11/52 ,  C08K5/098 ,  C08K3/22 ,  C08K5/07 ,  H01B13/00 ,  H01L21/288

CPC classification number: C08K5/17 ,  C08K3/22 ,  C08K5/07 ,  C08K5/098 ,  C08K2003/2248 ,  C09D11/037 ,  C09D11/38 ,  C09D11/52 ,  H01L21/288 ,  H01L21/4846 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49883 ,  H01L27/1085 ,  H01L28/60 ,  H01L2924/0002 ,  H05K3/105 ,  H05K3/4076 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09545 ,  H01L2924/00

Abstract: An object of the invention is to provide a simple method capable of easily forming a metal film on a surface of a perforated substrate that is adjacent to the hole in the substrate. The metal film forming method includes a step of heating a perforated substrate having a hole while a surface of the substrate adjacent to the hole is in contact with a conductive ink containing a metal salt and a reducing agent.

Abstract translation: 本发明的目的是提供一种能够容易地在与基板中的孔相邻的多孔基板的表面上形成金属膜的简单方法。 金属膜形成方法包括加热具有孔的多孔基材的步骤，同时邻近孔的基板的表面与含有金属盐和还原剂的导电油墨接触。

公开(公告)号：US20160050754A1

公开(公告)日：2016-02-18

申请号：US14823519

申请日：2015-08-11

Applicant: FANUC Corporation

Inventor： Makoto BEKKE

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K3/3447 ,  H05K2201/09545 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2203/044

Abstract: A printed wiring board includes three or more than three through holes. An inner wall of the through hole is covered by conductive coating. Same size leads of an electronic component are inserted into the through holes. The through holes are soldered by dip soldering the printed wiring board in melting solder. The through holes have two or more diameters. The diameter of the through hole having more adjacent through holes is not larger than the diameter of the through hole having less adjacent through holes.

Abstract translation: 印刷电路板包括三个或三个以上的通孔。 通孔的内壁被导电涂层覆盖。 将电子部件的相同尺寸的引线插入到通孔中。 通孔通过浸焊焊接印刷线路板而熔化焊料来焊接通孔。 通孔具有两个或更多个直径。 具有更多相邻通孔的通孔的直径不大于具有较少相邻通孔的通孔的直径。

公开(公告)号：US09107315B2

公开(公告)日：2015-08-11

申请号：US12582647

申请日：2009-10-20

Applicant: Chih-kuang Yang

Inventor： Chih-kuang Yang

IPC: H05K1/11 ,  H05K3/40 ,  H05K1/03 ,  H05K3/04

CPC classification number: H05K1/116 ,  H05K1/0393 ,  H05K1/115 ,  H05K3/048 ,  H05K3/4076 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09645 ,  H05K2201/09827 ,  Y10T29/49204

Abstract: Disclosed is a via structure in a multi-layer substrate, comprising a first metal layer, a dielectric layer and a second metal layer. The first metal layer has an upper surface. The dielectric layer covers the first metal layer in which a via is opened to expose the upper surface. The second metal layer is formed in the via and contacts an upper surface and an inclined wall of the via. A contacting surface of the second metal layer has a top line lower than the upper edge of the inclined wall. Alternatively, the second metal layer can be formed on the dielectric layer as being a metal line simultaneously as formed in the via as being a pad. The metal line and the pad are connected electronically. The aforesaid metal second layer can be formed in the via and on the dielectric layer by a metal lift-off process.

Abstract translation: 公开了一种多层基板中的通孔结构，包括第一金属层，电介质层和第二金属层。 第一金属层具有上表面。 电介质层覆盖第一金属层，其中通孔被打开以暴露上表面。 第二金属层形成在通孔中并与通孔的上表面和倾斜壁接触。 第二金属层的接触表面具有比倾斜壁的上边缘低的顶线。 或者，第二金属层可以作为金属线形成在电介质层上，同时形成在通孔中作为焊盘。 金属线和焊盘以电子方式连接。 上述金属第二层可以通过金属剥离工艺在通孔和电介质层上形成。

公开(公告)号：US09093767B2

公开(公告)日：2015-07-28

申请号：US13879883

申请日：2011-11-29

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01R31/06 ,  H01R13/24 ,  H05K3/32 ,  H05K3/40 ,  H05K7/10 ,  H05K3/10 ,  H05K3/12 ,  H05K1/14

CPC classification number: H01R23/6813 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01R12/73 ,  H01R12/82 ,  H01R13/2457 ,  H01R13/2485 ,  H01R31/06 ,  H05K1/092 ,  H05K1/111 ,  H05K1/141 ,  H05K1/182 ,  H05K3/0094 ,  H05K3/10 ,  H05K3/1291 ,  H05K3/326 ,  H05K3/363 ,  H05K3/365 ,  H05K3/4007 ,  H05K3/4015 ,  H05K3/4092 ,  H05K3/425 ,  H05K3/4694 ,  H05K7/1076 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/09381 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2201/10386 ,  H05K2201/2072 ,  H05K2201/209 ,  H05K2203/041 ,  H05K2203/1476 ,  Y10T29/49165 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A surface mount electrical interconnect adapted to provide an interface between solder balls on a BGA device and a PCB. The electrical interconnect includes a socket substrate with a first surface, a second surface, and a plurality of openings sized and configured to receive the solder balls on the BGA device. A plurality of electrically conductive contact tabs are bonded to the first surface of the socket substrate so that contact tips on the contact tabs extend into the openings. The contact tips electrically couple with the BGA device when the solder balls are positioned in the openings. Vias are located in the openings that electrically couple the contact tabs to contact pads located proximate the second surface of the socket substrate. Solder balls are bonded to the contact pad that are adapted to electrically and mechanically couple the electrical interconnect to the PCB.

Abstract translation: 适于在BGA器件上的焊球和PCB之间提供界面的表面贴装电互连。 电互连包括具有第一表面，第二表面和多个开口的插座基板，其尺寸和构造用于接收BGA器件上的焊球。 多个导电接触片接合到插座衬底的第一表面，使得接触片上的接触尖端延伸到开口中。 当焊球定位在开口中时，接触尖端与BGA器件电耦合。 通孔位于开口中，其将接触片电耦合到位于插座衬底的第二表面附近的接触垫。 焊球被接合到接触焊盘上，适于电连接和机械地将电互连件耦合到PCB。

公开(公告)号：US09059152B2

公开(公告)日：2015-06-16

申请号：US13659147

申请日：2012-10-24

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Masahiro Inoue ,  Atsuhiko Sugimoto

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/34 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81444 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H05K1/118 ,  H05K1/119 ,  H05K3/34 ,  H05K2201/09545 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Embodiments of the present invention provide a wiring substrate having a structure where a plurality of projection electrodes are arranged within an electrode formation region on a substrate main surface. At least one among a plurality of the projection electrodes is a variant projection electrode which has a recess portion on an upper surface, an outer diameter at the upper end that is larger than an outer diameter at the lower end, and a reverse trapezoidal cross-section shape. Embodiments of the present invention also provide methods for manufacturing wiring substrates having one or more of said variant projection electrode.

Abstract translation: 本发明的实施例提供一种布线基板，其具有多个突起电极布置在基板主表面上的电极形成区域内的结构。 多个突起电极中的至少一个是突起电极，其上表面具有凹部，上端的外径大于下端的外径，反向梯形截面， 截面形状。 本发明的实施例还提供了制造具有一个或多个所述变型投影电极的布线基板的方法。