公开(公告)号：US20170287808A1

公开(公告)日：2017-10-05

申请号：US15625947

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Feras EID ,  Adel A. ELSHERBINI ,  Johanna M. SWAN ,  Don W. NELSON

IPC: H01L23/498 ,  H01L23/367 ,  H01L21/52 ,  H01L23/473

CPC classification number: H01L23/3675 ,  H01L21/52 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/473 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5389 ,  H01L2924/0002 ,  H05K1/021 ,  H05K1/185 ,  H05K2201/066 ,  H05K2201/10416 ,  H05K2201/10545 ,  H01L2924/00

Abstract: An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.

公开(公告)号：US09717157B2

公开(公告)日：2017-07-25

申请号：US14617523

申请日：2015-02-09

Applicant: Micron Technology, Inc.

Inventor： Kevin Gibbons ,  Tracy V. Reynolds ,  David J. Corisis

IPC: H05K1/18 ,  H05K7/02 ,  H05K3/34 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H05K1/11 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19104 ,  H05K1/111 ,  H05K1/182 ,  H05K1/183 ,  H05K3/3436 ,  H05K7/02 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10727 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/4913 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. The computer modules can also include a microelectronic package carried by the module substrate. The microelectronic package includes a semiconductor die carried by a package substrate. At least a portion of the semiconductor die extends into the substrate material via the aperture.

公开(公告)号：US20170020011A1

公开(公告)日：2017-01-19

申请号：US15124602

申请日：2015-03-13

Applicant: TEXA S.p.A.

Inventor： Mauro Fantin ,  Igor Martinelli

IPC: H05K5/02 ,  H01R12/57 ,  G07C5/08 ,  H05K1/18 ,  H05K5/00 ,  G07C5/02 ,  H01R13/66 ,  H01R12/58

CPC classification number: H05K5/0247 ,  G07C5/02 ,  G07C5/08 ,  H01R12/57 ,  H01R12/58 ,  H01R13/665 ,  H01R13/6658 ,  H01R2201/26 ,  H05K1/117 ,  H05K1/181 ,  H05K5/0069 ,  H05K2201/09181 ,  H05K2201/1034 ,  H05K2201/10545

Abstract: Vehicle diagnostic interface module comprising: a printed circuit board, an OBD connector, which is provided with a plate-like contact-carrier socket arranged parallel to and facing the printed circuit board, a plurality of rigid pins, each of them having a first segment projecting from the inner face of the socket along an axis orthogonal to the printed circuit board and inserted in a notch formed on the outer perimeter edge of the board.

Abstract translation: 车辆诊断接口模块包括：印刷电路板，OBD连接器，其设置有平行于并面向印刷电路板的板状接触承载座，多个刚性销，每个具有第一段 从插座的内表面沿着与印刷电路板正交的轴突出并插入形成在板的外周边缘上的凹口中。

公开(公告)号：US09549461B2

公开(公告)日：2017-01-17

申请号：US14625440

申请日：2015-02-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masahiro Toyama ,  Motoo Suwa

IPC: H05K7/00 ,  H05K1/02

CPC classification number: H05K1/0231 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/025 ,  H05K2201/10545 ,  H01L2924/00012

Abstract: To improve electric characteristics of an electronic device. An electronic device includes a semiconductor device and a three-terminal capacitor mounted on the upper surface of a mounting substrate, the semiconductor device includes a power supply pad and a ground pad, the power supply pad and the ground pad are electrically connected with a power supply land and a ground land, respectively, and the power supply land and the ground land are allocated to a land line in an outermost periphery of the semiconductor device, Then, the power supply land and the ground land are electrically connected to the three-terminal capacitor by wirings formed on the upper surface of the mounting substrate.

Abstract translation: 改善电子设备的电气特性。 电子设备包括安装在安装基板的上表面上的半导体器件和三端电容器，该半导体器件包括电源焊盘和接地焊盘，电源焊盘和接地焊盘与电源电连接 分别供给地面和陆地，将电力供给用地和地面用地分配给半导体装置的最外周的陆线，然后，将电源用地和地面电连接到三相电源， 端子电容器通过布线形成在安装基板的上表面上。

公开(公告)号：US09480161B2

公开(公告)日：2016-10-25

申请号：US14158310

申请日：2014-01-17

Applicant: Freescale Semiconductor, Inc.

Inventor： Perry H. Pelley ,  Michael B. McShane ,  Tim V. Pham

IPC: H05K1/18 ,  H05K1/11 ,  H01L23/538 ,  H01L25/10 ,  H01L25/065 ,  H05K3/34 ,  G11C5/06

CPC classification number: H05K1/181 ,  G11C5/063 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/10 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/1434 ,  H05K3/3415 ,  H05K2201/097 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/10545 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (D1-D8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.

Abstract translation: 低剖面条双列直插式存储器模块（200）包括：被动中插支撑结构（90），其具有形成在相对的顶表面和底表面之间的图案化开口（91-97）;多个存储芯片（D1-D8） 顶表面和底表面以及垂直焊球导体（98），其延伸穿过图案化的开口以电连接多个存储器芯片，其中每个存储器芯片具有面向无源插入器结构的附接表面和水平导体的图案化阵列（例如， ，82-86），其形成在所述附接表面上，所述接触垫电连接到所述多个垂直导体，以限定电连接到所述第一和第二多个存储器管芯中的每个存储器管芯的至少一个总线导体。

公开(公告)号：US20160308330A1

公开(公告)日：2016-10-20

申请号：US14782980

申请日：2014-04-10

Applicant: Florent LIFFRAN ,  Olivier RABOT

Inventor： Florent LIFFRAN ,  Olivier RABOT

IPC: H01S5/042 ,  H03K3/57

CPC classification number: H01S5/0428 ,  H03K3/57 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/10015 ,  H05K2201/10174 ,  H05K2201/10446 ,  H05K2201/10545 ,  Y02P70/611

Abstract: The invention concerns a device for controlling at least one diode 2, the control device comprising an electrical card 4 comprising a printed circuit 5 on which the following are mounted: a diode 2, a front component 7 and a storage capacitor 9 connected in such a way as to form a circuit loop 17 extending substantially in a thickness of the electrical card 4.

Abstract translation: 本发明涉及一种用于控制至少一个二极管2的装置，该控制装置包括一个电子卡4，该电子卡包括印刷电路5，其上安装有以下装置：二极管2，前部组件7和存储电容器9， 以形成基本上以电卡4的厚度延伸的电路回路17。

公开(公告)号：US09457743B2

公开(公告)日：2016-10-04

申请号：US14230475

申请日：2014-03-31

Applicant: Johnson Controls Technology Company

Inventor： Edward J. Soleski ,  Mikhail S. Balk ,  Richard M. DeKeuster

IPC: B60R16/03 ,  H02J7/00 ,  G01R31/36 ,  H01M10/04 ,  H01M10/42 ,  H01M10/058 ,  H01M2/24 ,  H01M2/20 ,  H01M2/34 ,  H01H47/32 ,  H01M10/48 ,  H05K1/18 ,  H05K3/32 ,  B60L11/18 ,  H01M2/12 ,  H01M2/10 ,  H01R12/71 ,  H05K1/02 ,  H02H7/18 ,  G01R31/02

CPC classification number: H01M2/22 ,  B60L1/003 ,  B60L1/02 ,  B60L1/14 ,  B60L3/0046 ,  B60L3/12 ,  B60L11/123 ,  B60L11/14 ,  B60L11/1803 ,  B60L11/1851 ,  B60L11/1861 ,  B60L11/1864 ,  B60L11/1874 ,  B60L11/1877 ,  B60L11/1879 ,  B60L15/20 ,  B60L2210/10 ,  B60L2210/40 ,  B60L2240/34 ,  B60L2240/545 ,  B60L2240/547 ,  B60L2240/549 ,  B60L2250/10 ,  B60L2260/26 ,  B60L2270/20 ,  B60R16/03 ,  B60R16/033 ,  G01R31/025 ,  G01R31/362 ,  G01R31/3627 ,  H01H47/325 ,  H01M2/1077 ,  H01M2/1205 ,  H01M2/1211 ,  H01M2/1252 ,  H01M2/20 ,  H01M2/206 ,  H01M2/24 ,  H01M2/305 ,  H01M2/32 ,  H01M2/34 ,  H01M2/342 ,  H01M4/661 ,  H01M4/665 ,  H01M10/04 ,  H01M10/0413 ,  H01M10/058 ,  H01M10/425 ,  H01M10/4257 ,  H01M10/482 ,  H01M10/486 ,  H01M10/6551 ,  H01M2010/4271 ,  H01M2010/4278 ,  H01M2200/103 ,  H01M2220/20 ,  H01M2250/20 ,  H01R12/716 ,  H02H7/18 ,  H02J7/0021 ,  H02J7/0063 ,  H05K1/0262 ,  H05K1/0263 ,  H05K1/18 ,  H05K3/32 ,  H05K2201/10492 ,  H05K2201/1053 ,  H05K2201/10545 ,  Y02T10/6217 ,  Y02T10/645 ,  Y02T10/7005 ,  Y02T10/7016 ,  Y02T10/7044 ,  Y02T10/705 ,  Y02T10/7061 ,  Y02T10/7077 ,  Y02T10/7216 ,  Y02T10/7241 ,  Y02T10/7275 ,  Y10T29/49108 ,  Y10T29/4911 ,  Y10T29/49114

Abstract: A terminal for a battery module and a method of manufacture of the terminal are provided. The battery module may include a plurality of battery cells and a bus bar. The bus bar may be electrically coupled to the plurality of battery cells. The battery module also may include a battery terminal that carries a voltage from the bus bar. The battery terminal may include a generally cylindrical terminal portion and a connector. The connector may be coupled to the bus bar cell interconnect. The battery terminal also may include a bent portion. The bent portion is disposed between the terminal portion and the connector.

Abstract translation: 提供一种电池模块的端子和端子的制造方法。 电池模块可以包括多个电池单元和汇流条。 母线可以电耦合到多个电池单元。 电池模块还可以包括承载来自母线的电压的电池端子。 电池端子可以包括大致圆柱形的端子部分和连接器。 连接器可以耦合到汇流条单元互连。 电池端子也可以包括弯曲部分。 弯曲部分设置在端子部分和连接器之间。

公开(公告)号：US20160211190A1

公开(公告)日：2016-07-21

申请号：US14914998

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Henning BRAUNISCH ,  Feras EID ,  Adel A. ELSHERBINI ,  Johanna M. SWAN ,  Don W. NELSON

IPC: H01L23/367 ,  H01L21/52 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L21/52 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/473 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5389 ,  H01L2924/0002 ,  H05K1/021 ,  H05K1/185 ,  H05K2201/066 ,  H05K2201/10416 ,  H05K2201/10545 ,  H01L2924/00

Abstract: An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.

Abstract translation: 一种包括模具的设备，所述模具的第一侧包括第一类型的系统级接触点和包括第二类型的接触点的第二侧; 以及耦合到管芯和管芯的第二侧的封装衬底。 一种包括管芯的设备，所述管芯的第一侧包括多个系统级逻辑接触点和包括第二多个系统级电力接触点的第二侧。 一种方法，包括将管芯的第一侧上的第一类型的系统级接触点中的一个与管芯的第二侧上的第二类型的系统级接触点耦合到封装衬底。

公开(公告)号：US20160192497A1

公开(公告)日：2016-06-30

申请号：US14966280

申请日：2015-12-11

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Myung Lim RYU

IPC: H05K1/18 ,  H05K3/30 ,  H05K1/11

CPC classification number: H05K1/183 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L2224/16227 ,  H01L2924/1531 ,  H01L2924/19106 ,  H05K1/0271 ,  H05K3/284 ,  H05K2201/10545

Abstract: An electronic component module including a first board; a plurality of first electronic components disposed on a first surface of the first board; a second board disposed on a second surface of the first board, opposite to the one surface, to form a cavity; a third board disposed on the second surface of the first board to divide the cavity into a plurality of regions; and a plurality of second electronic components disposed in the regions and disposed on the second surface of the first board.

Abstract translation: 一种电子部件模块，包括第一板; 设置在所述第一板的第一表面上的多个第一电子部件; 设置在所述第一板的与所述一个表面相对的第二表面上的第二板，以形成空腔; 设置在所述第一板的所述第二表面上以将所述空腔分成多个区域的第三板; 以及设置在所述区域中并设置在所述第一板的第二表面上的多个第二电子部件。

公开(公告)号：US09377824B2

公开(公告)日：2016-06-28

申请号：US14244007

申请日：2014-04-03

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: G06F1/18 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/525 ,  H01L21/56 ,  H01L23/50 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L25/0657 ,  G06F1/18 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/525 ,  H01L23/5385 ,  H01L24/24 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104A, 105B, 107A, 107B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.

Abstract translation: 微电子组件（300）或系统（1500）包括至少一个微电子封装（100），所述微电子封装（100）具有面向上安装在衬底（102）的第一表面（108）上方的微电子元件（130），一个或多个柱 ，140）沿着所述微电子元件正面在第一方向（142）延伸的触点（132）。 在基板的第二表面（110）处露出的端子（1057a）的列（104A，105B，107A，107B）沿第一方向延伸。 具有宽度（152）不大于终端列的最小间距（150）的三分之一倍的中心区域（112）的表面（110）处的第一端子（105）可被配置为承载地址 用于确定可寻址存储器位置的信息。 微电子元件的轴向平面可以与中心区域相交。