公开(公告)号：US20150382456A1

公开(公告)日：2015-12-31

申请号：US14753165

申请日：2015-06-29

Applicant: FANUC CORPORATION

Inventor： Norihiro SAIDOU ,  Yuichi OKOUCHI

IPC: H05K1/02 ,  H05K3/34 ,  H05K1/18

CPC classification number: H05K3/3452 ,  H05K1/181 ,  H05K2201/09845 ,  H05K2203/0594 ,  H05K2203/1476

Abstract: A printed circuit board including a metal conductor formed on a surface of an insulating base material and having a component mounting portion, and a solder resist covering a part of the metal conductor, includes a thinned part on a component-mounting-portion side in the solder resist.

Abstract translation: 一种印刷电路板，包括形成在绝缘基材的表面上并具有部件安装部分的金属导体和覆盖金属导体的一部分的阻焊剂，包括在所述金属导体的部件安装部侧的薄化部分 阻焊剂

公开(公告)号：US09215798B2

公开(公告)日：2015-12-15

申请号：US14012173

申请日：2013-08-28

Applicant: Ronald Steven Cok

Inventor： Ronald Steven Cok

IPC: H01B13/00 ,  H05K1/02 ,  H05K3/46 ,  H05K3/12 ,  H05K3/00 ,  H05K1/09

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate, a first stamp, and a different multi-level second stamp. A curable bottom layer is provided over the substrate. One or more bottom-layer micro-channel(s) are imprinted in the curable bottom layer with the first stamp and a bottom-layer micro-wire formed in each bottom-layer micro-channel. A curable multi-layer is formed adjacent to and in contact with the cured bottom layer. First and second multi-layer micro-channels and a top-layer micro-channel are imprinted in the curable multi-layer with the multi-level second stamp. Either two bottom-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a top-layer micro-wire or two top-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a bottom-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供衬底，第一印模和不同的多级第二印模。 在基板上设置可固化的底层。 一个或多个底层微通道被印刷在可固化底层中，第一印模和底层微线形成在每个底层微通道中。 在固化的底层附近形成可固化的多层，并且与固化的底层接触。 第一和第二多层微通道和顶层微通道用多级第二印记印在可固化多层中。 两个底层微电线通过第一和第二多层微线电连接，并且顶层微线或两个顶层微线通过第一和第二多层微电子电连接 电线和底层微线。

公开(公告)号：US09197803B2

公开(公告)日：2015-11-24

申请号：US14483190

申请日：2014-09-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Nobuo Ikemoto ,  Atsushi Kumano ,  Jerry Hsieh ,  Jun Sasaki

IPC: H04N5/225 ,  H05K1/18 ,  H01L27/146 ,  H05K1/02

CPC classification number: H04N5/2257 ,  H01L27/14618 ,  H01L2224/16225 ,  H04N5/2253 ,  H04N5/2254 ,  H05K1/0298 ,  H05K1/182 ,  H05K1/185 ,  H05K2201/09845 ,  H05K2201/10121

Abstract: A camera module includes an image sensor IC, a resin multilayer board including thermoplastic resin layers stacked in a direction perpendicular or substantially perpendicular to a light receiving surface of the image sensor IC, a mounting electrode which is stacked on the thermoplastic resin layer and on which the image sensor IC is mounted, and a via-hole conductor electrically connected to the mounting electrode. The resin multilayer board includes a flat plate portion including a surface on which the mounting electrode is mounted, and a rigid portion including a greater number of thermoplastic resin layers than that of the flat plate portion, and the via-hole conductor is arranged in the flat plate portion so as to avoid the thermoplastic resin layer on which the mounting electrode is stacked.

Abstract translation: 相机模块包括图像传感器IC，包括沿垂直于或基本垂直于图像传感器IC的光接收表面的方向堆叠的热塑性树脂层的树脂多层板，堆叠在热塑性树脂层上的安装电极， 安装图像传感器IC，以及电连接到安装电极的通孔导体。 树脂多层板包括平板部分，其中安装有安装电极的表面和包含比平板部分多的热塑性树脂层的刚性部分，并且通孔导体布置在 平板部分，以避免堆叠安装电极的热塑性树脂层。

公开(公告)号：US20150282322A1

公开(公告)日：2015-10-01

申请号：US14659178

申请日：2015-03-16

Applicant: SEIKO EPSON CORPORATION

Inventor： Manabu KONDO

IPC: H05K1/18

CPC classification number: H05K1/18 ,  H05K1/0212 ,  H05K3/4697 ,  H05K2201/09845 ,  H05K2201/10068 ,  H05K2201/10075 ,  H05K2201/10151 ,  H05K2201/10219 ,  H05K2201/10515 ,  H05K2201/10553 ,  H05K2201/1056

Abstract: An electronic component includes a pedestal plate that has a first surface made of a metal and a second surface being an opposite surface to the first surface, a heating element arranged on the first surface of the pedestal plate, and a resonator element arranged on the heating element. The pedestal plate overlaps the resonator element in a plan view.

Abstract translation: 一种电子部件，包括具有由金属构成的第一表面和与第一表面相反的表面的第二表面的基座板，布置在基座板的第一表面上的加热元件和布置在加热器上的谐振元件 元件。 基座板在平面图中与谐振器元件重叠。

公开(公告)号：US20150244120A1

公开(公告)日：2015-08-27

申请号：US14708366

申请日：2015-05-11

Applicant: CommScope, Inc. of North Carolina

Inventor： Richard A. Schumacher ,  Scott Lynn Michaelis

IPC: H01R24/64 ,  H01R13/6463 ,  H01R13/627 ,  H01R13/42

CPC classification number: H01R24/64 ,  H01R12/53 ,  H01R13/6466 ,  H01R13/6469 ,  H01R13/665 ,  H01R13/6658 ,  H01R23/005 ,  H01R24/28 ,  H01R2107/00 ,  H01R2201/04 ,  H05K1/0245 ,  H05K1/115 ,  H05K1/117 ,  H05K2201/04 ,  H05K2201/0949 ,  H05K2201/09845 ,  H05K2201/1034 ,  H05K2201/10356 ,  Y10T29/49124

Abstract: Communications plugs are provided which include a printed circuit board having a plurality of elongated conductive traces and a plurality of plug blades. Each plug blade has a first section that extends along a top surface of the printed circuit board and a second section that extends along a front edge of the printed circuit board. Additionally, each plug blade may have a thickness that is at least twice the thickness of the elongated conductive traces. The plug blades may be low profile plug blades that are manufactured separately from the printed circuit board.

Abstract translation: 提供了通信插头，其包括具有多个细长导电迹线和多个插头片的印刷电路板。 每个插头片具有沿着印刷电路板的顶表面延伸的第一部分和沿着印刷电路板的前边缘延伸的第二部分。 此外，每个插头刀片可以具有至少是细长导电迹线的厚度的两倍的厚度。 插头片可以是与印刷电路板分开制造的低剖面插头片。

公开(公告)号：US09113565B2

公开(公告)日：2015-08-18

申请号：US14000566

申请日：2012-06-19

Applicant: Chuanzhi Li ,  Hua Miao ,  Zhanhao Xie ,  Jun Peng

Inventor： Chuanzhi Li ,  Hua Miao ,  Zhanhao Xie ,  Jun Peng

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K1/115 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0243 ,  H05K1/0298 ,  H05K3/0094 ,  H05K3/4635 ,  H05K2201/0792 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09618 ,  H05K2201/09845 ,  H05K2201/10242 ,  H05K2201/10416 ,  Y10T29/49165

Abstract: A printed circuit board (PCB), a method for processing PCB and an electronic apparatus. The method for processing PCB may comprise: forming a hole in the PCB, wherein the PCB includes a metal matrix and at least two substrate layers, at least one of the at least two substrate layers has a geoelectric layer thereon; and the metal matrix is fixed in a slot provided in the substrate, the formed hole contacts both the geoelectric layer and the metal matrix; and providing conductive substances in the hole, with the conductive substances in the hole being in contact with the inner geoelectric layer and the metal matrix, so that the geoelectric layer and the metal matrix are in conduction with each other.

Abstract translation: 印刷电路板（PCB），PCB的处理方法和电子设备。 用于处理PCB的方法可以包括：在PCB中形成孔，其中PCB包括金属基体和至少两个基底层，至少两个基底层中的至少一个在其上具有地电层; 并且所述金属基体固定在设置在所述基板中的槽内，所形成的孔与所述地电电极层和所述金属基体接触; 并且在孔中提供导电物质，孔中的导电物质与内部地电电极和金属基体接触，使得地电电介质层和金属基体彼此导通。

公开(公告)号：US20150230330A1

公开(公告)日：2015-08-13

申请号：US14619521

申请日：2015-02-11

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jyung Chan LEE ,  Eun Gu LEE ,  Sil Gu MUN ,  Sang Soo LEE

IPC: H05K1/02 ,  H05K3/36

CPC classification number: H05K1/0219 ,  H01P5/028 ,  H05K1/025 ,  H05K2201/0919 ,  H05K2201/09727 ,  H05K2201/09845 ,  H05K2201/10242 ,  Y10T29/49126

Abstract: A board assembly for transmitting a high-speed signal and a method of manufacturing the same. The board assembly may include a submount board, a base board, and a contact member for a signal line. The submount board may include at least one first high-speed signal line formed on the surface thereof. The base board may include the submount board on one part of the upper surface thereof, and at least second high-speed signal line on the other part of the upper surface thereof, wherein the second high-speed signal lines corresponds to the first high-speed signal lines, respectively. The contact member for the signal line may be installed on the side of the submount board, and have an upper portion contacting the first high-speed signal line and a lower portion contacting the second high-speed signal line such that the first high-speed signal line contacts the second high-speed signal line.

Abstract translation: 用于发送高速信号的电路板组件及其制造方法。 板组件可以包括副安装板，基板和用于信号线的接触构件。 副安装板可以包括形成在其表面上的至少一个第一高速信号线。 基板可以在其上表面的一部分上包括副安装板，并且在其上表面的另一部分上包括至少第二高速信号线，其中第二高速信号线对应于第一高速信号线， 速度信号线。 用于信号线的接触构件可以安装在副安装板的侧面上，并且具有接触第一高速信号线的上部和接触第二高速信号线的下部，使得第一高速信号线 信号线接触第二条高速信号线。

公开(公告)号：US20150228570A1

公开(公告)日：2015-08-13

申请号：US14697460

申请日：2015-04-27

Applicant: Invensas Corporation

Inventor： Valentin KOSENKO ,  Sergey SAVASTIOUK

IPC: H01L23/498 ,  H05K1/02 ,  H05K1/11

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/05 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/0195 ,  H05K2201/09563 ,  H05K2201/09845 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A through via (144) contains a conductor (244, 276) passing through a substrate (140) for connection to an integrated circuit element. The through via consists of two segments (144.1, 144.2) formed from respective different sides (140.1, 140.2) of the substrate and meeting inside the substrate. Each segment is shorter than the entire via, so via formation is facilitated. The second segment is etched after deposition of an etch stop layer (214) into the first segment. Due to the etch stop layer, the first segment's depth does not have to be rigidly controlled. The conductor is formed by separate depositions of conductive material into the via from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the via depth, so the deposition is facilitated. Other embodiments are also provided.

Abstract translation: 通孔（144）包含通过用于连接到集成电路元件的衬底（140）的导体（244,276）。 通孔包括由衬底的各个不同侧面（140.1,140.2）形成的两个段（144.1,144.2），并且在衬底内部会合。 每个段都比整个通孔短，因此通过形成便利。 在将蚀刻停止层（214）沉积到第一段中之后蚀刻第二段。 由于蚀刻停止层，第一段的深度不必严格控制。 导体由导电材料从衬底的每一侧分离成通孔而形成。 从每一侧，导体被沉积到比通孔深度更浅的深度，因此便于沉积。 还提供了其他实施例。

公开(公告)号：US09101056B2

公开(公告)日：2015-08-04

申请号：US14012240

申请日：2013-08-28

Applicant: Eastman Kodak Company

Inventor： Ronald Steven Cok

IPC: H01B13/00 ,  H05K1/02 ,  H05K3/46 ,  H05K3/12 ,  H05K3/00 ,  H05K1/09

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing a first stamp and a multi-level second stamp. A curable bottom layer and multi-layer are provided on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer. A multi-layer micro-channel and a top-layer micro-channel are imprinted in the multi-layer. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire extends from the central area into the edge area. The multi-layer micro-wire contacts the bottom-layer micro-wire in the edge area. The top-layer micro-wire is over the central area and is separate from the multi-layer micro-wire and the bottom-layer micro-channel. The bottom-layer micro-wire is electrically connected to the multi-layer micro-wire and is electrically isolated from the top-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供具有与边缘区域分离的边缘区域和中心区域的基板，并提供第一印模和多级第二印模。 在基板上设置有可固化的底层和多层。 底层微通道印在底层中。 多层微通道和顶层微通道印在多层中。 微线形成在每个微通道中。 底层微线从中心区域延伸到边缘区域。 多层微线接触边缘区域的底层微线。 顶层微线在中心区域之上，与多层微线和底层微通道分离。 底层微线电连接到多层微线，并与顶层微线电隔离。

公开(公告)号：US20150201500A1

公开(公告)日：2015-07-16

申请号：US14169169

申请日：2014-01-31

Applicant: Zohar SHINAR ,  Joel VIDAL

Inventor： Zohar SHINAR ,  Joel VIDAL

IPC: H05K3/12 ,  B29C67/00

CPC classification number: H05K3/125 ,  B29C64/112 ,  B29C64/135 ,  B29C64/386 ,  B29C70/882 ,  B29K2105/0058 ,  B29K2995/0005 ,  B29K2995/0007 ,  B29L2031/3406 ,  B29L2031/3425 ,  B33Y30/00 ,  B33Y50/02 ,  B33Y80/00 ,  H05K1/0206 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/0274 ,  H05K1/028 ,  H05K1/0281 ,  H05K1/0284 ,  H05K1/092 ,  H05K1/165 ,  H05K1/167 ,  H05K1/186 ,  H05K3/0005 ,  H05K3/1283 ,  H05K3/225 ,  H05K3/284 ,  H05K3/4007 ,  H05K3/4069 ,  H05K3/4664 ,  H05K3/4685 ,  H05K3/4688 ,  H05K2201/0367 ,  H05K2201/037 ,  H05K2201/0391 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/098 ,  H05K2201/09836 ,  H05K2201/09845 ,  H05K2201/09872 ,  H05K2201/10098 ,  H05K2203/013 ,  H05K2203/107 ,  H05K2203/163 ,  H05K2203/166

Abstract: Device, system, and method of three-dimensional printing. A device includes: a first 3D-printing head to selectively discharge conductive 3D-printing material; a second 3D-printing head to selectively discharge insulating 3D-printing material; and a processor to control operations of the first and second 3D-printing heads based on a computer-aided design (CAD) scheme describing a printed circuit board (PCB) intended for 3D-printing. A 3D-printer device utilizes 3D-printing methods, in order to 3D-print: (a) a functional multi-layer PCB; or (b) a functional stand-alone electric component; or (c) a functional PCB having an embedded or integrated electric component, both of them 3D-printed in a unified 3D-printing process.

Abstract translation: 三维打印的设备，系统和方法。 一种装置包括：第一3D打印头，用于选择性地排放导电3D打印材料; 第二3D打印头，用于选择性地放电绝缘3D打印材料; 以及基于描述用于3D打印的印刷电路板（PCB）的计算机辅助设计（CAD）方案来控制第一和第二3D打印头的操作的处理器。 3D打印机设备利用3D打印方法，以便3D打印：（a）功能性多层PCB; 或（b）功能独立电气部件; 或（c）具有嵌入或集成电气部件的功能PCB，它们都以统一的3D打印过程3D打印。