公开(公告)号：US20180368254A1

公开(公告)日：2018-12-20

申请号：US16109915

申请日：2018-08-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Toshiro ADACHI

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09 ,  H05K1/03 ,  H05K3/46 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K1/0271 ,  H05K1/0313 ,  H05K1/092 ,  H05K1/115 ,  H05K3/0011 ,  H05K3/4038 ,  H05K3/46 ,  H05K3/4644 ,  H05K2201/068 ,  H05K2201/095

Abstract: A resin substrate includes a first portion including a plurality of resin sheets provided at one end in a stacking direction and a second portion including a plurality of resin sheets provided at the other end in the stacking direction. The thickness of the plurality of resin sheets is the same or substantially the same as the thickness of the first portion and the second portion. The density of planar conductor patterns of the first portion with respect to the volume of the first portion is lower than the density of planar conductor patterns of the second portion with respect to the volume of the second portion. The average of the diameters of the first interlayer connection conductor provided in the first portion is greater than the average of the diameters of the second interlayer connection conductor provided in the second portion.

公开(公告)号：US20170318669A1

公开(公告)日：2017-11-02

申请号：US15649830

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Daniel Sobieski ,  Kyu Oh Lee ,  Sri Ranga Sai Boyapati

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/113 ,  H05K3/0041 ,  H05K3/181 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09218 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/096 ,  H05K2201/09654 ,  H05K2203/0548

Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.

公开(公告)号：US09769921B2

公开(公告)日：2017-09-19

申请号：US14732309

申请日：2015-06-05

Applicant: Tyco Electronics AMP Korea Ltd

Inventor： Yang Yoon Choi ,  Ok Ky Beak

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K3/06 ,  H05K3/46 ,  H05K3/42 ,  C25D5/02 ,  C23C18/16 ,  C23C18/54 ,  H05K3/38 ,  H05K3/00

CPC classification number: H05K1/0298 ,  C23C18/1637 ,  C23C18/1653 ,  C23C18/54 ,  C25D5/02 ,  H05K1/0206 ,  H05K1/0251 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/06 ,  H05K3/386 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/462 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0323 ,  H05K2201/095 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/073 ,  H05K2203/1476

Abstract: A printed circuit board has a double-sided substrate with an insulation layer, a bonding member, a base layer of an aluminum material, and a circuit pattern; a second insulation layer; a second bonding member; a second base layer; a through hole; a zinc substitution layer; a plating layer; and a second circuit pattern.

公开(公告)号：US09763327B2

公开(公告)日：2017-09-12

申请号：US14834180

申请日：2015-08-24

Applicant: Multek Technologies Ltd.

Inventor： Kwan Pen ,  Pui Yin Yu

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H05K3/00 ,  H05K3/06 ,  H05K3/18

CPC classification number: H05K1/115 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0058 ,  H05K3/06 ,  H05K3/181 ,  H05K3/188 ,  H05K3/42 ,  H05K3/422 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/095 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/10303

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

公开(公告)号：US20170156208A1

公开(公告)日：2017-06-01

申请号：US15431781

申请日：2017-02-14

Applicant: MEDIATEK INC.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H01L23/00 ,  H01L23/498 ,  H05K1/18 ,  H05K1/05

CPC classification number: H05K1/115 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/111 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic system includes a printed circuit board and a semiconductor package mounted on the printed circuit board. The printed circuit board includes a laminated core having an internal conductive layer and a build-up layer. The build-up layer includes a top conductive layer. Microvias are disposed in the build-up layer to connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

公开(公告)号：US09609749B2

公开(公告)日：2017-03-28

申请号：US14860718

申请日：2015-09-22

Applicant: MEDIATEK INC.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/115 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/111 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A printed circuit board includes a laminated core including at least an internal conductive layer, and a build-up layer on the laminated core. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area that is comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

公开(公告)号：US20170019998A1

公开(公告)日：2017-01-19

申请号：US14801422

申请日：2015-07-16

Applicant: Delphi Technologies, Inc.

Inventor： Rodrigo Franco

IPC: H05K1/14 ,  H05K1/11 ,  H05K3/40 ,  H05K3/36 ,  H05K3/42 ,  H05K1/18 ,  H05K3/32

CPC classification number: H05K1/144 ,  H05K1/111 ,  H05K1/115 ,  H05K1/14 ,  H05K1/141 ,  H05K1/145 ,  H05K1/181 ,  H05K1/183 ,  H05K3/32 ,  H05K3/3442 ,  H05K3/36 ,  H05K3/4007 ,  H05K3/429 ,  H05K2201/045 ,  H05K2201/09036 ,  H05K2201/09181 ,  H05K2201/095 ,  H05K2201/10166 ,  H05K2201/10727

Abstract: The circuit board assembly includes a first circuit board having a first plurality of electronic components attached to a major surface of the first circuit board. The first plurality of electronic components is electrically interconnected to a first plurality of conductive pads defined on the major surface of the first circuit board. A second circuit board has a second plurality of electronic components attached to a first major surface of the second circuit board. The second plurality of electronic components is electrically interconnected to a second plurality of conductive pads defined on a second major surface of the second circuit board. The first and second circuit board are attached by coupling the first and second plurality of conductive pads. A portion of the first plurality of electronic components on the first circuit board are disposed within a cavity defined by the second major surface of the second circuit board.

Abstract translation: 电路板组件包括具有附接到第一电路板的主表面的第一多个电子部件的第一电路板。 第一组多个电子部件电连接到限定在第一电路板的主表面上的第一多个导电焊盘。 第二电路板具有附接到第二电路板的第一主表面的第二多个电子部件。 所述第二多个电子部件电连接到限定在所述第二电路板的第二主表面上的第二多个导电焊盘。 第一和第二电路板通过联接第一和第二多个导电焊盘而附接。 第一电路板上的第一多个电子部件的一部分设置在由第二电路板的第二主表面限定的空腔内。

公开(公告)号：US20160372958A1

公开(公告)日：2016-12-22

申请号：US15163389

申请日：2016-05-24

Applicant: LG INNOTEK CO., LTD.

Inventor： Young Kil Song

IPC: H02J7/02 ,  H05K1/02 ,  H02J7/00 ,  H05K1/18

CPC classification number: H02J7/025 ,  H02J7/0042 ,  H02J50/10 ,  H02J50/70 ,  H05K1/0216 ,  H05K1/0296 ,  H05K1/14 ,  H05K1/181 ,  H05K3/32 ,  H05K3/341 ,  H05K3/3415 ,  H05K7/02 ,  H05K2201/095

Abstract: A wireless charging device includes a transmitter configured to transmit a power signal for wireless charging, a circuit board including at least one component configured to control an operation of the transmitter, a shielding plate configured to block an electrical interference between the transmitter and the circuit board, and a connector configured to penetrate through the circuit board and the shielding plate so as to electrically connect the transmitter with the at least one component.

Abstract translation: 无线充电装置包括：发射机，被配置为发送用于无线充电的功率信号;电路板，包括配置成控制发射机的操作的至少一个部件;被配置为阻挡发射机和电路板之间的电气干扰的屏蔽板 以及连接器，被配置为穿透所述电路板和所述屏蔽板，以将所述发射器与所述至少一个部件电连接。

公开(公告)号：US20150342053A1

公开(公告)日：2015-11-26

申请号：US14815184

申请日：2015-07-31

Applicant: Cisco Technology, Inc.

Inventor： Jovica Savic ,  Zhiping Yang ,  Jie Xue ,  Li Li

IPC: H05K1/18 ,  H05K1/11 ,  H01L23/498

CPC classification number: H05K1/183 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/095 ,  H05K2201/10492 ,  H05K2201/10507 ,  H01L2924/00

Abstract: An apparatus includes a cavity formed in a support structure, the support structure being operable to support a semiconductor device. A circuit element is disposed in the cavity in the support structure, and the cavity in the support structure is filled with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material. The semiconductor device is electrically connected to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.

Abstract translation: 一种装置包括形成在支撑结构中的空腔，所述支撑结构可操作以支撑半导体器件。 电路元件设置在支撑结构中的空腔中，并且支撑结构中的空腔填充有不导电的填充材料，以便至少部分地围绕电路元件与非导电填充材料。 半导体器件电连接到电路元件。 在示例性实施例中，电路元件可操作以基本上阻挡由半导体器件或另一半导体器件输出的直流电流。

公开(公告)号：US20150296624A1

公开(公告)日：2015-10-15

申请号：US14438660

申请日：2013-05-09

Applicant: LG INNOTEK CO., LTD.

Inventor： Yun Ho An ,  Won Suk Jung ,  Ran Kim ,  Sung Soo Park ,  Young Joon Son ,  Sang Myung Lee ,  Woo Young Lee ,  Joon Wook Han

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/09136 ,  H05K2201/095 ,  H05K2201/0959 ,  H05K2201/10636 ,  H05K2203/0191 ,  Y02P70/611

Abstract: A printed circuit board for mounting a chip includes: a core layer including a chip mounting cavity; a chip mounted into the chip mounting cavity; a first insulating material layer filled in a space between the chip mounting cavity and the chip; and a second insulating material layer laminated on one surface of the core layer.

Abstract translation: 用于安装芯片的印刷电路板包括：芯层，包括芯片安装腔; 芯片安装在芯片安装腔中; 填充在芯片安装腔和芯片之间的空间中的第一绝缘材料层; 以及层叠在芯层的一个表面上的第二绝缘材料层。