Patent search cpc:"H05K2201/09609" Page 6

51.

发明授权
Optical transceiver, connector, substrate unit, optical transmitter, optical receiver, and semiconductor device 失效
Title translation: 光收发器，连接器，基板单元，光发射器，光接收器和半导体器件

公开(公告)号：US06937824B2

公开(公告)日：2005-08-30

申请号：US10307285

申请日：2002-12-02

Applicant: Toshiaki Watanabe

Inventor： Toshiaki Watanabe

IPC: H01S5/022 , G02B6/42 , H01L31/0232 , H04B10/2507 , H04B10/40 , H04B10/50 , H04B10/60 , H05K1/02 , H05K1/14 , H05K3/34 , G02B6/36 , H04B10/02 , H04B10/12

CPC classification number: H05K1/141 , G02B6/4201 , G02B6/4246 , H05K1/0219 , H05K1/024 , H05K3/3447 , H05K2201/09609 , H05K2201/09809 , H05K2201/10303 , H05K2201/10371 , H05K2201/10424 , H05K2201/1059

Abstract: One ends of a plurality of interface pins are attached to a substrate in a line. Optical semiconductor device and an electric circuit are mounted on this substrate. The other ends of the interface pins are fit into holes in an another substrate. Signals are exchanged between the two substrates via the interface pins. The interface pins are embedded in a dielectric material. A plurality of ground pins and/or ground through holes may be provided in the dielectric material around the interface pins. The dielectric constant of the dielectric material is less than the dielectric constants of the two substrates.

Abstract translation: 多个接口引脚的一端以一行连接到基板。光学半导体器件和电路安装在该衬底上。接口引脚的另一端装配在另一个基板上的孔中。信号通过接口引脚在两个基板之间交换。接口引脚嵌入电介质材料中。多个接地引脚和/或接地通孔可以设置在接口引脚周围的电介质材料中。介电材料的介电常数小于两个基片的介电常数。

52.

发明授权
High density microvia substrate with high wireability 失效
Title translation: 具有高线性的高密度微孔基材

公开(公告)号：US06919635B2

公开(公告)日：2005-07-19

申请号：US10701311

申请日：2003-11-04

Applicant: Kazushige Kawasaki , Irving Memis

Inventor： Kazushige Kawasaki , Irving Memis

IPC: H05K1/18 , H01L23/12 , H01L23/498 , H05K1/02 , H05K1/03 , H05K1/11 , H05K3/46 , H01L23/48

CPC classification number: H01L23/49838 , H01L23/49822 , H01L2224/16 , H01L2924/0102 , H01L2924/01078 , H01L2924/15311 , H01L2924/3025 , H05K1/0366 , H05K1/112 , H05K1/115 , H05K3/4602 , H05K3/4626 , H05K2201/029 , H05K2201/09609 , H05K2201/09627

Abstract: The density of plated thru holes in a glass fiber based chip carrier is increased by off-setting holes to positions in which fibers from adjacent holes will not connect. Elongated strip zones or regions having a width approximately the diameter of the holes and running along orthogonal columns and rows of holes, parallel to the direction of fibers, define regions of fibers that can possibly cause shorting between holes. Rotating a conventional X-Y grid pattern of equidistant holes so as to position, for example, alternate holes in one direction between the elongated strip zones running in the opposite direction significantly increases the distance between holes along the elongated strip zones running in each direction. The holes are positioned between elongated strip zones with sufficient clearance to compensate for variations in the linear path of fibers.

Abstract translation: 基于玻璃纤维的芯片载体中的电镀通孔的密度通过偏移孔增加到相邻孔的纤维将不连接的位置。宽度大约为孔的宽度的区域或区域平行于纤维方向的正交列和孔排沿着孔的直径延伸，限定了可能导致孔之间短路的纤维区域。旋转等距孔的常规X-Y网格图案，以便例如在沿相反方向运行的细长条带之间的一个方向上的交替孔定位显着地增加沿着沿每个方向运行的细长条带的孔之间的距离。孔位于具有足够间隙的细长带区之间以补偿纤维线性路径的变化。

53.

发明授权
Semiconductor package insulation film and manufacturing method thereof 有权
Title translation: 半导体封装绝缘膜及其制造方法

公开(公告)号：US06894374B2

公开(公告)日：2005-05-17

申请号：US10621771

申请日：2003-07-17

Applicant: Makoto Yoshino , Kenji Masumoto

Inventor： Makoto Yoshino , Kenji Masumoto

IPC: H01L21/48 , H01L23/31 , H01L23/498 , H05K1/00 , H05K3/00 , H01L23/495

CPC classification number: H01L24/97 , H01L21/486 , H01L23/3128 , H01L23/49827 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01078 , H01L2924/15311 , H01L2924/181 , H05K1/0393 , H05K3/0097 , H05K2201/09609 , H05K2203/1545 , H01L2224/85 , H01L2924/00012 , H01L2224/45015 , H01L2924/207

Abstract: An insulation film for providing an insulation substrate carrying a semiconductor chip of a semiconductor package. Insulation film 10 is provided with rows of opposing sprocket holes 12 formed on either edge of the above mentioned insulation film, and through holes 14 are disposed two-dimensionally between the rows of sprocket holes 12. Pitch p between through holes 14 is determined by the relationship mp=nL (i.e., n and m are integers, and n

Abstract translation: 一种用于提供承载半导体封装的半导体芯片的绝缘衬底的绝缘膜。绝缘膜10设置有形成在上述绝缘膜的任一边缘上的一排相对的链轮孔12，并且通孔14二维设置在链轮孔12的行之间。通孔14之间的间距p由关系mp = nL（即，n和m是整数，n

54.

发明授权
Semiconductor package insulation film and manufacturing method thereof 有权
Title translation: 半导体封装绝缘膜及其制造方法

公开(公告)号：US06875637B2

公开(公告)日：2005-04-05

申请号：US09909013

申请日：2001-07-19

Applicant: Makoto Yoshino , Kenji Masumoto

Inventor： Makoto Yoshino , Kenji Masumoto

IPC: H01L23/12 , H01L21/48 , H01L21/60 , H01L23/31 , H01L23/498 , H05K1/00 , H05K3/00 , H01L21/50 , H01L21/46

CPC classification number: H05K3/0097 , H01L21/486 , H01L23/3128 , H01L23/49827 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01078 , H01L2924/15311 , H01L2924/181 , H05K1/0393 , H05K2201/09609 , H05K2203/1545 , H01L2224/85 , H01L2224/45015 , H01L2924/207 , H01L2924/00012

Abstract: An insulation film for providing an insulation substrate carrying a semiconductor chip of a semiconductor package. Insulation film 10 is provided with rows of opposing sprocket holes 12 formed on either edge of the above mentioned insulation film, and through holes 14 are disposed two-dimensionally between the rows of sprocket holes 12. Pitch p between through holes 14 is determined by the relationship m p=n L (i.e., n and m are integers, and n

Abstract translation: 一种用于提供承载半导体封装的半导体芯片的绝缘衬底的绝缘膜。绝缘膜10设置有形成在上述绝缘膜的任一边缘上的一排相对的链轮孔12，并且通孔14二维地设置在链轮孔12之间。通孔14之间的间距p由关系mp = n L（即，n和m是整数，n

55.

发明申请
Module with built-in circuit component and method for producing the same 有权
Title translation: 具有内置电路元件的模块及其制造方法

公开(公告)号：US20040226744A1

公开(公告)日：2004-11-18

申请号：US10844823

申请日：2004-05-12

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Toshiyuki Asahi , Yutaka Taguchi , Yasuhiro Sugaya , Seiichi Nakatani , Toshio Fujii

IPC: H05K007/06

CPC classification number: H05K1/186 , H01L25/165 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/97 , H01L2924/19105 , H05K1/115 , H05K3/20 , H05K3/4614 , H05K2201/09609 , H05K2201/09618 , H05K2201/10378 , H05K2203/061 , H01L2224/81 , H01L2224/83

Abstract: A module with a built-in circuit component of the present invention includes an electric insulating layer, a pair of wiring layers provided on both principal planes of the electric insulating layer, a plurality of via conductors electrically connecting the pair of wiring layers and passing through the electric insulating layer in a thickness direction thereof, and a circuit component buried in the electric insulating layer, wherein the plurality of via conductors are disposed in a circumferential portion of the electric insulating layer in accordance with a predetermined rule. The plurality of via conductors are placed at an interval, for example, so as to form at least one straight line, in a cut surface of the electric insulating layer in a direction parallel to a principal plane thereof.

Abstract translation: 具有本发明的内置电路部件的模块包括电绝缘层，设置在电绝缘层的两个主平面上的一对布线层，多个通孔导体，电连接该对布线层并通过所述电绝缘层的厚度方向以及埋设在所述电绝缘层中的电路部件，其中，所述多个通孔导体按照规定的规则配置在所述电绝缘层的周向部分。多个通孔导体例如在与绝缘层的主平面平行的方向上在电绝缘层的切割面上形成至少一条直线的间隔。

56.

发明申请
Standardized circuit board core 审中-公开
Title translation: 标准化电路板芯

公开(公告)号：US20040178000A1

公开(公告)日：2004-09-16

申请号：US10655845

申请日：2003-09-04

Inventor： Tzyy-Jang Tseng

IPC: H05K001/11

CPC classification number: H05K3/4602 , H05K1/0287 , H05K1/0298 , H05K3/4069 , H05K3/4614 , H05K3/4652 , H05K2201/09609 , H05K2201/09945

Abstract: A standardized or partial standardized circuit board core comprises at least a dielectric core layer and a plurality of conductive posts, in which the dielectric layer has a first surface and a related second surface. The conductive posts pass through the dielectric core layer and connect to the first and second surfaces of the dielectric layer respectively. The conductive posts are array arranged or arranged in a constant distance form in the dielectric core layer. Moreover, the standardized or partial standardized circuit board core further includes two conductive layers, which are covered on the first and second surfaces of the dielectric core layer.

Abstract translation: 标准化或部分标准化电路板芯包括至少介电芯层和多个导电柱，其中介电层具有第一表面和相关的第二表面。导电柱穿过介质芯层并分别连接到电介质层的第一和第二表面。导电柱在介质芯层中以恒定距离的形式排列或布置。此外，标准化或部分标准化电路板芯还包括两个导电层，其被覆在介质芯层的第一和第二表面上。

57.

发明授权
Circuit boards containing vias and methods for producing same 有权

公开(公告)号：US06774486B2

公开(公告)日：2004-08-10

申请号：US09974947

申请日：2001-10-10

Applicant: Larry D. Kinsman

Inventor： Larry D. Kinsman

IPC: H01L2348

CPC classification number: H05K1/115 , H01L23/49827 , H01L2924/0002 , H05K3/4602 , H05K2201/0949 , H05K2201/09609 , H05K2201/09836 , H05K2201/09945 , H01L2924/00

Abstract: The present invention is directed to an apparatus and method for connecting integrated circuits placed on opposite sides of a circuit board through utilization of conduction elements embedded in the circuit board and extending from one surface of the board to the other. Conductive traces extend along the surface of the circuit board from the conduction elements to the integrated circuits. The conductive traces may be formed from multiple conductive layers.