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    Method of fabricating a parallel processor package
    83.
    发明授权
    Method of fabricating a parallel processor package 失效
    制造并行处理器封装的方法

    公开(公告)号：US5346117A

    公开(公告)日：1994-09-13

    申请号：US97604

    申请日：1993-07-27

    Applicant: Harold Kohn ,  Donald J. Lazzarini

    Inventor： Harold Kohn ,  Donald J. Lazzarini

    IPC: G06F13/40 ,  H05K1/00 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46 ,  H05K3/36

    CPC classification number: H05K3/4635 ,  G06F13/409 ,  H05K3/462 ,  H05K1/0393 ,  H05K2201/0305 ,  H05K2201/0373 ,  H05K2201/09536 ,  H05K2201/09572 ,  H05K2201/096 ,  H05K2201/10159 ,  H05K3/328 ,  H05K3/4038 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4641 ,  Y10T29/49126

    Abstract: Disclosed is a method for manufacturing a stacked circuitized flex structure. The structure is a laminate for Z-axis communication within a parallel processor. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. Z-axis circuitization is carried out by providing vias and through holes in individual circuitized flex strips. These vias and through holes are circuited and plated. This is followed by filling the vias and through holes with solder and forming solder bumps at the tops and bottoms of the vias and through holes. A sticker sheet with clearance holes for the solder bumps is provided, and a plurality of the circuitized flex strips are laid up for lamination to form a stack of circuitized flexible strips. Lamination is carried out at elevated pressure and temperature to crush the solder bumps, bond, and homogenize solder bump material and fuse the sticker sheets. Next, the stack is cooled to solidify the homogenized solder bump material.

    Abstract translation: 公开了一种用于制造堆叠电路化柔性结构的方法。 该结构是在并行处理器内用于Z轴通信的层压板。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 通过在单独的电路化柔性条中设置通孔和通孔来进行Z轴电路化。 这些通孔和通孔被循环和电镀。 然后在通孔和通孔的顶部和底部填充通孔和通孔用焊料和形成焊料凸块。 提供了具有用于焊料凸块的间隙孔的贴纸，并且堆叠多个电路化的柔性条以层压以形成电路化的柔性条的堆叠。 层压在升高的压力和温度下进行，以粉碎焊料凸块，粘合和均质焊料凸块材料并熔合贴纸。 接下来，将堆叠冷却以固化均质化的焊料凸块材料。

    Method of making chip resistors and in the chip resistors resulting from the method
    84.
    发明授权
    Method of making chip resistors and in the chip resistors resulting from the method 失效
    制造芯片电阻的方法和由该方法产生的片式电阻器

    公开(公告)号：US4646057A

    公开(公告)日：1987-02-24

    申请号：US702021

    申请日：1985-02-15

    Applicant: Quentin M. Reynolds

    Inventor： Quentin M. Reynolds

    IPC: H01C1/14 ,  H01C1/144 ,  H01C7/00 ,  H01C17/00 ,  H01C17/24 ,  H01C17/242 ,  H01C17/28 ,  H05K3/34 ,  H01G1/14

    CPC classification number: H05K3/3442 ,  H01C1/144 ,  H01C17/006 ,  H01C17/242 ,  H01C17/28 ,  H05K2201/09181 ,  H05K2201/09572 ,  H05K2201/10636 ,  H05K2201/10984 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49099 ,  Y10T29/49101 ,  Y10T29/49147 ,  Y10T29/49165

    Abstract: A method of forming chip resistors in which a resistive coating is applied to an insulating substrate which is subsequently divided up into single chip components includes the step of providing end terminations for the individual chip resistors before the sheet is divided up. This is achieved by forming a hole 13 in the substrate 11 at the position of each end termination and then coating the holes with an electrically conductive material 14 which electrically connects with the adjacent region of the resistive coating 12. In order to improve the solderability and the reliability of the end terminations the holes 13 may be filled with solder 15. The electrical value of the resistive element coating may then be adjusted to a precise value by trimming away some of the resistive element material with a laser. Finally, the substrate is divided up into the single chip resistor components.

    Abstract translation: 一种形成片状电阻器的方法，其中将电阻涂层施加到绝缘衬底上，该绝缘衬底随后被分成单个芯片部件，包括在片材被分割之前为各个芯片电阻器提供端接端的步骤。 这是通过在每个端部端子的位置处在基板11中形成孔13，然后用与电阻涂层12的相邻区域电连接的导电材料14涂覆孔来实现的。为了改善可焊性和 可以用焊料15填充孔13的端部端接的可靠性。然后可以通过用激光器去除一些电阻元件材料来将电阻元件涂层的电气值调整到精确的值。 最后，将基板分为单片电阻器组件。

    Vacuum-heat treatment of printed circuit boards
    85.
    发明授权
    Vacuum-heat treatment of printed circuit boards 失效
    印刷电路板的真空热处理

    公开(公告)号：US3708876A

    公开(公告)日：1973-01-09

    申请号：US3708876D

    申请日：1969-01-28

    Applicant: BURROUGHS CORP

    Inventor： KLEHM W

    IPC: H05K3/00 ,  B41M3/08

    CPC classification number: H05K3/0011 ,  H05K3/0055 ,  H05K2201/09572 ,  H05K2203/083 ,  H05K2203/085 ,  H05K2203/1105 ,  Y10T29/49155

    Abstract: Relates to the avoidance of electrical discontinuities arising in the production of two-sided printed circuit boards having plated-through-holes and particularly occurring in the use of solder for improving the electrical interconnections. Research disclosed that the cause of these discontinuities lay in the material of the boards surrounding the holes which either included entrapped gas or matter vaporizable under the high temperatures of the liquid solder applied to fill the holes to assure reliable plated-through-hole connections. A vacuum evaporation operation was incorporated in the fabrication process and found highly useful and efficient in the production of reliable hole connections substantially reducing if not completely eliminating any need to apply solder touch-ups to the boards thereafter. Specifically, the boards were treated prior to the soldering of the plated-through holes to a temperature of approximately 250* F while concurrently being exposed to a vacuum of approximately 10 2 mm Hg for a sufficient time to drive out of the boards all matter vaporizable under such conditions.

    Abstract translation: 关于避免在制造具有电镀通孔的双面印刷电路板中出现的电中断，并且特别是在使用焊料来改善电互连的情况下。 研究公开了这些不连续性的原因在于围绕孔的板材的材料，其包括在被施加以填充孔的液体焊料的高温下被包埋的气体或物质可蒸发，以确保可靠的电镀通孔连接。 在制造过程中并入真空蒸发操作，并且发现在生产可靠的孔连接方面非常有用和高效，这大大减少，如果不能完全消除任何需要在其后对板进行焊接接触。 具体来说，在将电镀通孔焊接到约250°F的温度之前将板处理，同时暴露于大约10 -2mm Hg的真空足够的时间以驱出板 所有物质在这种条件下可蒸发。

    High-Current PCB Traces
    89.
    发明申请
    High-Current PCB Traces 审中-公开

    公开(公告)号：US20170311440A1

    公开(公告)日：2017-10-26

    申请号：US15491727

    申请日：2017-04-19

    Applicant: Schweitzer Engineering Laboratories, Inc.

    Inventor： Travis C. Mallett ,  Ben M. Armstrong ,  Forrest A. Rahrer

    IPC: H05K1/02 ,  H05K1/11 ,  H05K3/40

    CPC classification number: H05K1/0265 ,  H05K1/0206 ,  H05K3/429 ,  H05K2201/09572

    Abstract: The present disclosure relates to systems and methods using thermal vias to increase the current-carrying capacity of conductive traces on a multilayered printed circuit board (PCB). In various embodiments, parameters associated with vias may be selected to control various electrical and thermal properties of the conductive trace. Such parameters include the via diameter, a plating thickness, a number of vias, a placement of the vias, an amount of conductive material to be added or removed from the conductive trace, a change in the resistance of the conductive trace, a change in a fusing measurement of the conductive trace, and the like.

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