公开(公告)号：US20160353576A1

公开(公告)日：2016-12-01

申请号：US15163032

申请日：2016-05-24

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yasuhiko Kusama ,  Hironobu Hashimoto ,  Takeshi Chino ,  Kazuhiro Kobayashi

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/32 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H05K1/02 ,  H05K3/40

CPC classification number: H01L23/3142 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4697 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10378

Abstract: An electronic component built-in substrate includes an insulating base material having a first surface and a second surface opposite to the first surface, an electronic component embedded in the insulating base material and having an electrode on a side surface thereof, a first wiring layer embedded in an area outside the electrode of the electronic component in the insulating base material with a surface of the first wiring layer being exposed from the first surface of the insulating base material, a via conductor reaching from the second surface of the insulating base material to a side surface of the electrode of the electronic component and the first wiring layer, and a second wiring layer formed on the second surface of the insulating base material and connected to the via conductor.

Abstract translation: 电子部件内置基板包括具有第一表面和与第一表面相对的第二表面的绝缘基材，嵌入绝缘基材中并在其侧表面上具有电极的电子部件，嵌入的第一布线层 在所述绝缘基材中的所述电子部件的电极外的区域中，所述第一布线层的表面从所述绝缘基材的第一表面露出，所述通孔导体从所述绝缘基材的第二表面到达 电子部件的电极的侧表面和第一布线层，以及形成在绝缘基材的第二表面上并连接到通孔导体的第二布线层。

公开(公告)号：US20160336262A1

公开(公告)日：2016-11-17

申请号：US15219803

申请日：2016-07-26

Applicant: FUJIFILM Corporation

Inventor： Kosuke YAMASHITA

IPC: H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H05K3/40 ,  H05K3/46 ,  H05K1/02 ,  H05K1/03

CPC classification number: H01L23/49838 ,  C23C18/00 ,  C23C18/1653 ,  C23C18/54 ,  C25D3/00 ,  C25D3/38 ,  C25D5/48 ,  C25D11/045 ,  C25D11/08 ,  C25D11/12 ,  C25D11/16 ,  C25D11/20 ,  C25F3/20 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/144 ,  H05K3/368 ,  H05K3/4038 ,  H05K3/4611 ,  H05K2201/042 ,  H05K2201/10378 ,  H05K2203/0315

Abstract: The present invention is to provide a microstructure capable of improving the withstand voltage of an insulating substrate while securing fine conductive paths, a multilayer wiring board, a semiconductor package, and a microstructure manufacturing method. The microstructure of the present invention has an insulating substrate having a plurality of through holes, and conductive paths consisting of a conductive material containing metal filling the plurality of through holes, in which an average opening diameter of the plurality of through holes is 5 nm to 500 nm, an average value of the shortest distances connecting the through holes adjacent to each other is 10 nm to 300 nm, and a moisture content is 0.005% or less with respect to the total mass of the microstructure.

Abstract translation: 本发明提供一种能够在确保精细导电路径的同时提高绝缘基板的耐电压的微结构，多层布线基板，半导体封装以及微结构制造方法。 本发明的微细结构具有绝缘基板，具有多个贯通孔，导电路径由含有填充多个贯通孔的金属的导电材料构成，其中多个通孔的平均开口直径为5nm〜 连接相邻的通孔的最短距离的平均值为10nm〜300nm，水分含量相对于微结构的总质量为0.005％以下。

公开(公告)号：US20160329273A1

公开(公告)日：2016-11-10

申请号：US15214532

申请日：2016-07-20

Applicant: Dai Nippon Printing Co., Ltd.

Inventor： Takamasa Takano

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/1579 ,  H05K1/113 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/09436 ,  H05K2201/09581 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2203/0733 ,  H05K2203/1178 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49165 ,  H01L2224/05647 ,  H01L2924/01024 ,  H01L2924/01079

Abstract: A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.

公开(公告)号：US09491847B2

公开(公告)日：2016-11-08

申请号：US14921867

申请日：2015-10-23

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sang Soo Park ,  Byoung Hwa Lee ,  Young Ghyu Ahn ,  Heung Kil Park ,  Hyun Sub Oh

IPC: H01G4/224 ,  H05K1/02 ,  H01G4/12 ,  H01G4/236 ,  H01G4/30 ,  H05K1/18 ,  H05K1/03

CPC classification number: H05K1/0213 ,  H01G2/04 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/232 ,  H01G4/236 ,  H01G4/30 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/2045

Abstract: A multilayer ceramic electronic component includes: a board including first and second contact terminals disposed on one surface thereof to be spaced apart from each other and first and second external terminals disposed on the other surface thereof to be spaced apart from each other; a multilayer ceramic capacitor including first and second external electrodes including first and second connection portions disposed on opposite end surfaces of a ceramic body and first and second band portions extending from the first and second connection portions to portions of one surface of the ceramic body and connected to the first and second contact terminals, respectively; a sealing part enclosing the multilayer ceramic capacitor on the board while exposing one ends of the first and second contact terminals; and first and second connection terminals connecting the ends of the first and second contact terminals to the first and second external terminals, respectively.

Abstract translation: 多层陶瓷电子部件包括：板，其包括设置在其一个表面上的彼此间隔开的第一和第二接触端子，以及设置在另一个表面上的第一和第二外部端子彼此间隔开; 包括第一和第二外部电极的多层陶瓷电容器，所述第一和第二外部电极包括设置在陶瓷体的相对端面上的第一和第二连接部分以及从第一和第二连接部分延伸到陶瓷体的一个表面的部分的第一和第二带部分， 分别连接到第一和第二接触端子; 密封部分，其将所述多层陶瓷电容器封装在所述板上，同时暴露所述第一和第二接触端子的一端; 以及分别将第一和第二接触端子的端部连接到第一和第二外部端子的第一和第二连接端子。

公开(公告)号：US20160316565A1

公开(公告)日：2016-10-27

申请号：US14695057

申请日：2015-04-24

Applicant: Unimicron Technology Corp.

Inventor： Yin-Ju CHEN ,  Ming-Hao WU ,  Cheng-Po YU

IPC: H05K1/18 ,  H05K1/11 ,  H01L35/30 ,  H05K3/30 ,  H05K3/40 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K3/4647 ,  G06F1/206 ,  H01L23/12 ,  H01L23/13 ,  H01L23/4275 ,  H01L23/49827 ,  H01L35/30 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15153 ,  H01L2924/15313 ,  H05K1/0203 ,  H05K1/0206 ,  H05K1/113 ,  H05K1/14 ,  H05K1/181 ,  H05K1/185 ,  H05K1/187 ,  H05K3/36 ,  H05K3/4697 ,  H05K2201/048 ,  H05K2201/10219 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10734

Abstract: A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface.

公开(公告)号：US09480161B2

公开(公告)日：2016-10-25

申请号：US14158310

申请日：2014-01-17

Applicant: Freescale Semiconductor, Inc.

Inventor： Perry H. Pelley ,  Michael B. McShane ,  Tim V. Pham

IPC: H05K1/18 ,  H05K1/11 ,  H01L23/538 ,  H01L25/10 ,  H01L25/065 ,  H05K3/34 ,  G11C5/06

CPC classification number: H05K1/181 ,  G11C5/063 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/10 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/1434 ,  H05K3/3415 ,  H05K2201/097 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/10545 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (D1-D8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.

Abstract translation: 低剖面条双列直插式存储器模块（200）包括：被动中插支撑结构（90），其具有形成在相对的顶表面和底表面之间的图案化开口（91-97）;多个存储芯片（D1-D8） 顶表面和底表面以及垂直焊球导体（98），其延伸穿过图案化的开口以电连接多个存储器芯片，其中每个存储器芯片具有面向无源插入器结构的附接表面和水平导体的图案化阵列（例如， ，82-86），其形成在所述附接表面上，所述接触垫电连接到所述多个垂直导体，以限定电连接到所述第一和第二多个存储器管芯中的每个存储器管芯的至少一个总线导体。

公开(公告)号：US20160309578A1

公开(公告)日：2016-10-20

申请号：US14992904

申请日：2016-01-11

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Heung Kil PARK

IPC: H05K1/02 ,  H05K1/18 ,  H01G4/30 ,  H01G4/248 ,  H01G4/12 ,  H01G4/012

CPC classification number: H01G4/248 ,  H01G2/06 ,  H01G4/012 ,  H01G4/232 ,  H01G4/30 ,  H01G4/38 ,  H01L41/053 ,  H01L41/083 ,  H05K1/0306 ,  H05K1/141 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/1053 ,  H05K2201/10962

Abstract: A capacitor component includes a capacitor including a plurality of internal electrodes, a capacitor body containing a piezoelectric material disposed in at least regions between the plurality of internal electrodes, and external electrodes connected to the plurality of internal electrodes; and an interposer disposed to be coupled to the capacitor and including a buffer substrate containing a buffer material having a degree of piezoelectricity lower than that of the piezoelectric material, and connection electrodes electrically connected to the external electrodes.

Abstract translation: 电容器部件包括：包括多个内部电极的电容器;包含设置在所述多个内部电极之间的至少区域中的压电材料的电容器体以及与所述多个内部电极连接的外部电极; 以及插入器，其设置成耦合到所述电容器并且包括缓冲基板，所述缓冲基板包含压电度低于所述压电材料的缓冲材料，以及电连接到所述外部电极的连接电极。

公开(公告)号：US09474156B2

公开(公告)日：2016-10-18

申请号：US13492895

申请日：2012-06-10

Applicant: Greg Fosnes ,  Aaron Miletich ,  Chris Ligtenberg ,  Jay Anastas ,  Erik James Shahoian ,  Eric Knopf ,  Peter Arnold

Inventor： Greg Fosnes ,  Aaron Miletich ,  Chris Ligtenberg ,  Jay Anastas ,  Erik James Shahoian ,  Eric Knopf ,  Peter Arnold

IPC: H05K7/00 ,  H05K1/14 ,  H01R12/73 ,  H05K3/36

CPC classification number: H05K1/141 ,  H01R12/73 ,  H05K1/144 ,  H05K3/368 ,  H05K2201/0311 ,  H05K2201/042 ,  H05K2201/09027 ,  H05K2201/09063 ,  H05K2201/10378 ,  H05K2201/10409 ,  H05K2203/167 ,  Y10T29/49147

Abstract: Non-rectangular or rectangular interposers for space efficient, reliable to manufacture, high speed interconnections between two printed circuit boards, such as a motherboard and a mating board. One example provides space efficiency with a non-rectangular interposer, where the interposer may be at least approximately circular. Reliable manufacturing may be provided by the inclusion of one or more openings to accept one or more alignment features. In one example, a first opening is provided to accept a threaded boss, which may be used to fasten the two printed circuit boards and interposer together. In another example, a second opening may be provided to accept an alignment post, wherein the post aligns the interposer to the two printed circuit boards. Contacts may be provided on each side to mate with contacts on each of the two printed circuit boards.

Abstract translation: 非矩形或矩形内插器，用于空间高效，可靠地制造，两个印刷电路板（如主板和配对板）之间的高速互连。 一个示例使用非矩形插入器提供空间效率，其中插入件可以至少近似为圆形。 可以通过包括一个或多个开口来接受一个或多个对准特征来提供可靠的制造。 在一个示例中，提供第一开口以接纳螺纹凸台，其可用于将两个印刷电路板和插入件紧固在一起。 在另一示例中，可以提供第二开口以接受对准柱，其中柱将插入件对准到两个印刷电路板。 可以在每一侧设置触点以与两个印刷电路板中的每一个上的触点配合。

公开(公告)号：US09460989B2

公开(公告)日：2016-10-04

申请号：US14183188

申请日：2014-02-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Wei Liang ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Chia-Chun Miao ,  Chun-Lin Lu

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/485 ,  G06F17/50 ,  H01L21/768 ,  H01L23/14 ,  H05K1/11 ,  H05K1/02

CPC classification number: H01L23/485 ,  G06F17/5068 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/115 ,  H05K2201/068 ,  H05K2201/09781 ,  H05K2201/10378

Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.

Abstract translation: 一种结构包括具有多个球的衬底，半导体芯片和电连接衬底和半导体芯片的插入器。 所述插入器包括第一侧，与所述第一侧相对的第二侧，至少一个第一排除区域，所述至少一个第一排除区域延伸穿过所述多个球的每个球上方的所述插入器，至少一个主动通孔，其从所述插入件的第一侧延伸到 其中所述至少一个活性通孔形成在所述至少一个第一排除区域的外部，并且其中在所述至少一个第一排除区域内没有形成活性通孔，以及至少一个虚拟通孔， 所述插入器的第一侧到所述插入件的第二侧，其中所述至少一个虚拟通孔形成在所述至少一个第一排除区域内。

公开(公告)号：US09456503B2

公开(公告)日：2016-09-27

申请号：US14209106

申请日：2014-03-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tadashi Nomura ,  Akihiko Kamada

IPC: H05K1/18 ,  H05K3/28 ,  H05K1/03 ,  H05K1/14

CPC classification number: H05K3/284 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/09063 ,  H05K2201/09154 ,  H05K2201/09163 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10378 ,  H05K2201/2018 ,  H05K2201/2072 ,  H05K2203/063 ,  H05K2203/1327 ,  Y10T29/49146 ,  H01L2924/00014

Abstract: An engagement structure for preventing the separation of a resin layer is formed in a contact surface of an insulating substrate in a connecting component, the contact surface being in contact with the resin layer. The resin layer engages with the engagement structure in the contact surface in the insulating substrate in contact with the resin layer, the contact surface forming the side surface of the connecting component.

Abstract translation: 在连接部件中的绝缘基板的接触面上形成防止树脂层分离的接合结构，该接触面与树脂层接触。 树脂层与绝缘基板的与树脂层接触的接触表面中的接合结构接合，接触表面形成连接部件的侧表面。