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    Method and system for assessing reliability of integrated circuit
    5.
    发明专利
    Method and system for assessing reliability of integrated circuit 有权
    用于评估集成电路可靠性的方法和系统

    公开(公告)号：JP2011040725A

    公开(公告)日：2011-02-24

    申请号：JP2010158143

    申请日：2010-07-12

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： FEN CHEN ,  FENG KAI D ,  HE ZHONG-XIANG

    IPC: H01L21/8234 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092

    CPC classification number: G01R31/2621 ,  G01R31/2855 ,  G01R31/2894

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit system for assessing reliability of an integrated circuit having many field-effect-transistors. SOLUTION: This invention provides the method. The method includes: operating a plurality of field-effect-transistors (FETs) under a first operation condition; reversing an operation direction for at least one of the plurality of FETs for a brief period of time; measuring a second operation condition of the one of the plurality of FETs during the brief period of time; computing a difference between the second operation condition and a reference operation condition; and providing a reliability indicator based upon the difference between the second and the reference operation conditions, wherein the plurality of FETs are employed in a single integrated circuit (IC). COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于评估具有许多场效应晶体管的集成电路的可靠性的方法和电路系统。 解决方案：本发明提供了该方法。 该方法包括：在第一操作条件下操作多个场效应晶体管（FET）; 短时间内反转多个FET中的至少一个的操作方向; 在短时间内测量所述多个FET中的一个的第二操作条件; 计算第二操作条件和参考操作条件之间的差; 以及基于所述第二参考操作条件和所述参考操作条件之间的差异提供可靠性指示器，其中所述多个FET用于单个集成电路（IC）。 版权所有（C）2011，JPO＆INPIT

    Device, and method (mim capacitor and its manufacturing method)
    6.
    发明专利
    Device, and method (mim capacitor and its manufacturing method) 有权
    装置和方法（MIM电容器及其制造方法）

    公开(公告)号：JP2008004939A

    公开(公告)日：2008-01-10

    申请号：JP2007160933

    申请日：2007-06-19

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： HE ZHONG-XIANG ,  ESHUN EBENEZER E ,  DOUGLAS D COOLBAUGH ,  RASSEL ROBERT MARK

    IPC: H01L21/822 ,  H01L21/3205 ,  H01L23/52 ,  H01L27/04

    CPC classification number: H01L28/60

    Abstract: PROBLEM TO BE SOLVED: To provide an MIM capacitor device and a method for manufacturing it. SOLUTION: This device includes: an upper plate which comprises one or more conductive layers and has an upper surface, a lower surface and a side wall; a spreader plate which comprises one or more conductive layers and has an upper surface, a lower surface and a side wall; and a dielectric block which comprises one or more dielectric layers and has an upper surface, a lower surface and a side wall. The upper surface of the dielectric block is physically in contact with the lower surface of the upper plate. The lower surface of the dielectric block is above the upper surface of the spreader plate. The side wall of the upper plate and the dielectric block is essentially coplanar. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种MIM电容器装置及其制造方法。 解决方案：该装置包括：上板，其包括一个或多个导电层，并具有上表面，下表面和侧壁; 包括一个或多个导电层并具有上表面，下表面和侧壁的扩展板; 以及包括一个或多个电介质层并具有上表面，下表面和侧壁的介电块。 介质块的上表面物理地与上板的下表面接触。 介质块的下表面在扩展板的上表面之上。 上板和介质块的侧壁基本上是共面的。 版权所有（C）2008，JPO＆INPIT

    On-chip inductor with magnetic core
    7.
    发明专利
    On-chip inductor with magnetic core 有权
    带磁芯的片上电感器

    公开(公告)号：JP2006013111A

    公开(公告)日：2006-01-12

    申请号：JP2004187571

    申请日：2004-06-25

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： DING HANYI ,  FENG KAI D ,  HE ZHONG-XIANG ,  LIU XUEFENG

    IPC: H01F17/04 ,  H01F27/28 ,  H01F27/42 ,  H01F37/00 ,  H01F41/04

    Abstract: PROBLEM TO BE SOLVED: To provide an inductor being formed on an integrated circuit chip.
    SOLUTION: The on-chip inductor comprises one or a plurality of inner layers (12) existing between two or more outer layers (14), an inductor metal wiring turn (16) included in the one or a plurality of inner layers (12), and a magnetic member for forming the two or more outer layers (14) and the one or a plurality of inner layers (12). In one embodiment, the magnetic member is photoresist paste containing magnetic particles. In another embodiment, the magnetic member is a series of magnetic metal strips (32 and 36) arranged, respectively, on the first and second parts (30 and 34) of the two or more outer layers (14) and on the one or a plurality of inner layers (12), respectively. The series of magnetic metal strips on the first and second parts (30 and 34) form a lattice pattern. Other mode includes deposition of a compound controlled adjustably and a control winding having an adjustable current.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供形成在集成电路芯片上的电感器。 片上电感器包括存在于两个或多个外层（14）之间的一个或多个内层（12），包含在一个或多个内层（14）中的电感器金属布线匝（16） （12），以及用于形成所述两个或更多个外层（14）和所述一个或多个内层（12）的磁性构件。 在一个实施例中，磁性构件是含有磁性颗粒的光致抗蚀剂浆料。 在另一个实施例中，磁性构件是分别布置在两个或多个外层（14）的第一和第二部分（30和34）上并且在一个或多个外层（14）上的一系列磁性金属条（32和36） 多个内层（12）。 第一和第二部分（30和34）上的一系列磁性金属条形成格子图案。 其他模式包括可调整控制的化合物的沉积和具有可调电流的控制绕组。 版权所有（C）2006，JPO＆NCIPI

    METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION
    9.
    发明申请
    METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION 审中-公开
    金属绝缘体 - 金属电容器和制造方法

    公开(公告)号：WO2005034201A3

    公开(公告)日：2007-12-06

    申请号：PCT/US2004032405

    申请日：2004-09-30

    Applicant: IBM ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

    Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

    IPC: H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC classification number: H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interievel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interievel dielectric layer, atop surface of the bottom electrode co-planer with a top surface of the interievel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

    Abstract translation: 一种MIM电容器的方法和结构，所述结构包括：电子器件，包括：形成在半导体衬底上的电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的顶表面具有所述电介质层的顶表面; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。 导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。 还公开了兼容的电阻器和对准标记结构。

    INTERDIGITATED VERTICAL PARALLEL CAPACITOR
    10.
    发明申请
    INTERDIGITATED VERTICAL PARALLEL CAPACITOR 审中-公开
    INTERDIGITATED垂直并联电容器

    公开(公告)号：WO2011031512A3

    公开(公告)日：2011-06-23

    申请号：PCT/US2010046742

    申请日：2010-08-26

    Applicant: IBM ,  BOOTH JR ROGER A ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG

    Inventor： BOOTH JR ROGER A ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG

    IPC: H01L27/108 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02

    CPC classification number: H01L28/90 ,  H01L23/5223 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

    Abstract translation: 叉指结构可以包括至少一个第一金属线，平行于至少一个第一金属线并与至少一个第一金属线分离的至少一个第二金属线，以及接触该至少一个第一金属线的端部的第三金属线 第一金属线并与所述至少一个第二金属线分离。 所述至少一个第一金属线不垂直接触任何金属通孔，并且至少一个第二金属线可垂直接触至少一个金属通孔。 多层交错结构可以垂直堆叠。 替代地，叉指结构可以包括多个第一金属线和多个第二金属线，每条金属线不垂直地接触任何金属通孔。 交叉结构的多个实例可以横向复制和邻接，具有或不具有旋转和/或垂直堆叠以形成电容器。

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