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公开(公告)号：CN105959005A
公开(公告)日：2016-09-21
申请号：CN201610248384.8
申请日：2016-04-20
Applicant: 北京交通大学
CPC classification number: H03M1/1023 , H03M1/38 , H03M2201/76
Abstract: 本发明提供了一种流水线ADC的数字后台校准装置。该装置包括多级级联的子流水线和校准电路组成，每级子流水线包括采样/保持电路，余量放大器，Sub‑ADC与Sub‑DAC，模拟信号依次通过流水线ADC的每一级子流水线，在模拟量输入被校准级子流水线的同时，校准电路产生的伪随机序列被输入到被校准级子流水线的Sub‑DAC中，校准电路利用伪随机序列和被校准级子流水线的所有后级子流水线转换的校准后的数字量，对被校准级子流水线转换的数字量进行校准，得到被校准级子流水线转换的校准后的数字量。本发明克服现有校准算法对模拟电路的修改，可同时校准由电容失配与运放有限增益引起的误差，且不打断ADC正常的工作，不改变原有模拟电路设计，特别是较好改进了由于校准算法本身引入的误差，校准代价小，校准精度高。
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公开(公告)号：KR1020070111163A
公开(公告)日：2007-11-21
申请号：KR1020060044183
申请日：2006-05-17
Applicant: 고려대학교 산학협력단
CPC classification number: H03M1/14 , H03K3/02 , H03M1/002 , H03M2201/6107 , H03M2201/76
Abstract: A programmable clock generator and a pipelined converter using the same are provided to use a clock signal having an optimum duty ratio by changing a control voltage according to power consumption, thereby minimizing the power consumption. A first programmable inverter(410) is connected to a reference clock at both input terminals, and varies a period in which the reference clock is inverted. An inverter(420) is connected to the reference clock to inverter the reference clock. A second programmable inverter(430) is connected to an input terminal of the inverter to vary a period in which the signal of the input terminal is inverted. First and second latch circuits(440,450) have set inputs connected to the reference clock and the inverter and reset inputs connected to the output of the first and the second programmable inverters, respectively.
Abstract translation: 提供了一种可编程时钟发生器和使用该可编程时钟发生器的流水线转换器，以通过根据功耗改变控制电压来使用具有最佳占空比的时钟信号，从而最小化功耗。 第一可编程反相器（410）在两个输入端子处连接到参考时钟，并且改变参考时钟反相的周期。 逆变器（420）连接到参考时钟以使参考时钟反相。 第二可编程逆变器（430）连接到逆变器的输入端，以改变输入端的信号反转的周期。 第一和第二锁存电路（440,450）分别具有连接到参考时钟和反相器的设置输入和连接到第一和第二可编程反相器的输出的复位输入。
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公开(公告)号：KR1020060109397A
公开(公告)日：2006-10-20
申请号：KR1020060094476
申请日：2006-09-28
Applicant: 이종우
Inventor： 이종우
CPC classification number: H03M1/1235 , G06F7/00 , H03M1/002 , H03M1/14 , H03M2201/196 , H03M2201/534 , H03M2201/76
Abstract: A pipeline analog to digital converter to implement a logarithmic function is provided to introduce a pipeline structure for performing a conversion by a relatively fixed reference voltage without influence of a device characteristic or an environment. A method for implementing a pipeline analog to digital converter to implement a logarithmic function includes the steps of: implementing an analog digital converter by using a basic mathematical relation of the logarithmic function; calculating an amplification ratio of a differential amplifier and a reference voltage formula; constituting a circuit by only a scalar product without using a product function circuit; constructing a dependent circuit of 1.5 bit structure; calculating final 8 bit data by calculating the generated 1.5 bit digital signal; dividing into two stages to correct the large amplification ratio at the first stage; and correcting errors by measuring a polarity determined through the comparator before a sample/hold circuit again.
Abstract translation: 提供了一种用于实现对数函数的管线模数转换器，用于引入用于通过相对固定的参考电压执行转换的流水线结构，而不受设备特性或环境的影响。 一种用于实现流水线模数转换器以实现对数函数的方法包括以下步骤：通过使用对数函数的基本数学关系实现模拟数字转换器; 计算差分放大器的放大比和参考电压公式; 仅使用标量产品构成电路，而不使用产品功能电路; 构建1.5比特结构的依赖电路; 通过计算生成的1.5位数字信号计算最终的8位数据; 分为两个阶段，以纠正第一阶段的大放大率; 并且通过在再次采样/保持电路之前测量通过比较器确定的极性来校正误差。
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公开(公告)号：KR1020090093145A
公开(公告)日：2009-09-02
申请号：KR1020080018503
申请日：2008-02-28
Applicant: 재단법인서울대학교산학협력재단
CPC classification number: H03M1/14 , H03M1/361 , H03M1/662 , H03M2201/2216 , H03M2201/6309 , H03M2201/76
Abstract: A multiplying digital to analog converter and pipelined analog to a digital converter having the same are provided to obtain a desired value in a first timing by making the pipeline analog digital convertor have high gain in second timing. In a multiplying digital to analog converter and pipelined analog to a digital converter having the same, a sample/hold part(110) receives an analog signal. The sample/hold part produces an analog input signal by performing the sampling and holding calculation. A stage unit(120) receives analog input signal, and the stage part outputs a digital stage output power signal consisting of 1.5 bit or 2 bit. The stage part is divided into a first stage including a multiplying digital to analog converter and a second stage(122b) not including the multiplying digital to analog converter.
Abstract translation: 提供一个乘法数模转换器和流水线模拟到具有该数字转换器的数字转换器，以通过使得流水线模拟数字转换器在第二定时具有高增益来在第一定时中获得期望值。 在乘法数模转换器和具有相同数字转换器的流水线模拟转换器中，采样/保持部分（110）接收模拟信号。 采样/保持部分通过执行采样和保持计算产生模拟输入信号。 舞台单元（120）接收模拟输入信号，舞台部分输出由1.5位或2位组成的数字级输出功率信号。 舞台部分被分为包括乘法数模转换器的第一级和不包括乘法数模转换器的第二级（122b）。
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公开(公告)号：KR1020050066929A
公开(公告)日：2005-06-30
申请号：KR1020040011197
申请日：2004-02-20
Applicant: 한국전자통신연구원
IPC: H03M1/14
CPC classification number: H03M1/141 , H03M1/0607 , H03M2201/61 , H03M2201/76
Abstract: 본 발명은 아날로그-디지털 변환기에 관한 발명이다. 특히, 파이프라인 폴딩 구조의 아날로그-디지털 변환기에 관한 발명이다.
본 발명에 의한 파이프라인 폴딩 구조의 아날로그-디지털 변환기는 아날로그 입력 전압을 샘플링하여 출력하는 제 1 샘플-앤드-홀드부, 기준전압들을 발생시키는 기준전압 발생기, 상기 제 1 샘플-앤드-홀드부의 출력에 각 기준전압을 뺀 값들을 증폭하여 출력하되, 증폭기의 비대칭성으로 인한 오프셋의 영향을 제거한 선행 증폭기, 상기 선행 증폭기의 출력을 폴딩하여 출력하는 제 1 폴더, 상기 제 1 폴더의 출력을 샘플링하여 출력하는 제 2 샘플-앤드-홀드부, 상기 제 2 샘플-앤드-홀드부의 출력을 폴딩하여 출력하는 제 2 폴더, 및 상기 선행 증폭기의 출력 및 상기 제 2 폴더의 출력값을 비교 연산하여 디지털 출력값을 구하는 비교기를 포함한다.
본 발명에 의한 파이프라인 폴딩 구조의 아날로그-디지털 변환기는 특히 소자의 부정합으로 의하여 발생하는 오프셋을 제거함으로써, 고해상도의 아날로그-디지털 변환기를 구현할 수 있다는 장점이 있다.-
Patent Agency Ranking
公开(公告)号：KR1020140063059A
公开(公告)日：2014-05-27
申请号：KR1020120129957
申请日：2012-11-16
Applicant: 서강대학교산학협력단
IPC: H03M1/38
CPC classification number: H03M1/14 , H03M1/361 , H03M1/38 , H03M2201/2216 , H03M2201/2233 , H03M2201/76
Abstract: The present invention relates to a pipelined ADC. A first end thereof is configured to be formed by two SAR ADC which is provided in a dual channel and the remaining end thereof is configured to be formed by a first flash ADC and a second flash ADC which are provided in a single channel. The present invention is capable of rapid operation because a Nyquist input signal is appropriately processed even without a secure hash algorithm (SHA) and simultaneously the speed of the operation is not limited by the SAR ADC.
Abstract translation: 本发明涉及流水线ADC。 其第一端被配置成由设置在双通道中的两个SAR ADC形成，其另一端被配置为由设置在单个通道中的第一闪存ADC和第二闪存ADC形成。 本发明能够快速操作，因为即使没有安全散列算法（SHA）也适当地处理奈奎斯特输入信号，并且同时运行速度不受SAR ADC的限制。
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公开(公告)号：KR1020110108562A
公开(公告)日：2011-10-06
申请号：KR1020100027824
申请日：2010-03-29
Applicant: 서강대학교산학협력단
IPC: H03M1/14
CPC classification number: H03M1/14 , H03M1/002 , H03M1/1245 , H03M1/361 , H03M1/662 , H03M2201/2216 , H03M2201/61 , H03M2201/76
Abstract: 본 발명은 파이프라인 구조의 ADC에 관한 것으로서, 복수의 FLASH ADC들과 복수의 MDAC들을 포함하는 N(N은 자연수) 단으로 구성된 파이프라인 구조의 ADC에 있어서, 첫 번째 단의 제 1 FLASH ADC와 첫 번째 단의 제 1 MDAC의 입력단 샘플링 스위치에 동일한 게이트 부트스트래핑 회로를 적용하는 것을 특징으로 하며, 샘플링 부정합 현상을 최소화하는 동시에 신호의 왜곡 없이 입력 신호를 샘플링할 수 있으며, 증폭기의 개수를 최소한으로 사용하여 전체 전력 소모를 줄일 수 있다.
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公开(公告)号：KR1020090011099A
公开(公告)日：2009-02-02
申请号：KR1020070074353
申请日：2007-07-25
Applicant: 고려대학교 산학협력단 , 전북대학교산학협력단
IPC: H03M1/12
CPC classification number: H03M1/0617 , H03M1/002 , H03M1/1009 , H03M1/122 , H03M1/14 , H03M2201/6107 , H03M2201/76
Abstract: An analog to digital converter removing a memory effect is provided to reduce power consumption by sharing an operational amplifier composed of a plurality of input terminals. A pipeline analog to digital has the multiple stages in which a sample mode and a hold mode are alternated. A folded-cascode amplifier including a cascode amplifier is applied in a pair of stages among the plurality of stages. In the pair of stages, the input terminal of the folded-cascode amplifier is connected when the state with high significance is in a hold mode and the input terminal of the cascode amplifier is connected when the stage with low significance is in the hold mode.
Abstract translation: 通过共享由多个输入端组成的运算放大器来提供消除存储器效应的模数转换器来降低功耗。 模拟到数字管线具有交替采样模式和保持模式的多个阶段。 包括共源共栅放大器的折叠共源共栅放大器被施加在多个级之间的一对级中。 在一对级中，当具有高有效性的状态处于保持模式时，折叠共源共栅放大器的输入端连接，并且当具有低重要性的级处于保持模式时，共源共栅放大器的输入端连接。
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公开(公告)号：KR101783318B1
公开(公告)日：2017-09-29
申请号：KR1020160073693
申请日：2016-06-14
Applicant: 울산과학기술원
CPC classification number: H03M1/004 , H03M1/002 , H03M1/122 , H03M1/38 , H03M2201/76
Abstract: 본발명은아날로그-디지털변환장치에관한것으로, 아날로그신호를입력받아채널별다중화신호로출력하는다중화부와, 상기다중화부로부터출력되는상기다중화신호를디지털변환한후 순환(cyclic)시키는순환변환모드, 또는상기다중화신호를디지털변환한후 종속된(cascaded) 다음단으로전달하는파이프라인(pipeline) 변환모드를선택적으로수행하는아날로그-디지털변환부와, 상기순환변환모드에의해디지털변환된다중화신호또는상기파이프라인변환모드에의해디지털변환된다중화신호를단일신호로출력하는인터페이스부를포함할수 있다.
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公开(公告)号：KR1020140000365A
公开(公告)日：2014-01-03
申请号：KR1020120067091
申请日：2012-06-22
Applicant: 한국과학기술원
IPC: H03M1/12
CPC classification number: H03M1/361 , H03M1/002 , H03M1/127 , H03M1/129 , H03M1/14 , H03M2201/2216 , H03M2201/62 , H03M2201/76
Abstract: The present invention relates to a pipeline analog to digital converter (ADC) comprising: an ADC module including N (N is natural number) sub modules discriminating analog input signals according to signal size intervals and performing digital conversion, and making some of the sub modules amplify a residual voltage to a range larger than an amplitude range of the analog input signals and transfer the amplified voltage to the next sub module; a clock signal generator for providing clock signals for the digital conversion to the N ADC modules; and a digital correction circuit for receiving the digital signal from the N ADC modules, correcting the received digital signal, and outputting the digital signal with M (M is natural number) bits.
Abstract translation: 本发明涉及一种流水线模数转换器（ADC），包括：包括N（N为自然数）子模块的ADC模块，根据信号尺寸间隔区分模拟输入信号并执行数字转换，并使一些子模块 将残余电压放大到大于模拟输入信号的幅度范围的范围，并将放大的电压传送到下一个子模块; 时钟信号发生器，用于向N个ADC模块提供数字转换的时钟信号; 以及数字校正电路，用于从N个ADC模块接收数字信号，校正接收到的数字信号，并以M（M为自然数）位输出数字信号。
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