公开(公告)号：KR1020030047565A

公开(公告)日：2003-06-18

申请号：KR1020010078268

申请日：2001-12-11

Applicant: 한국전자통신연구원

Inventor： 한선호 ,  최장홍 ,  장재홍 ,  유현규

IPC: H03L7/00

CPC classification number: H03M7/3022 ,  H03L7/1978

Abstract: PURPOSE: A structure of a delta sigma divider is provided to obtain the capacity to synthesize the broadband frequency and maximize an effect of a delta sigma method by adding an output value of a delta sigma modulator to an external input value to modulate a value of a swallow counter. CONSTITUTION: A delta sigma modulator(41) is used for receiving a frequency and an external input value. A swallow adder block(40) is used for adding an external input value to an output value of the delta sigma modulator. A program register block(37) is used for storing an output value of the swallow adder block. A pulse swallow counter block(34) is formed with a dual modulus prescaler, a program counter, and a swallow counter in order to divide an input frequency according to a stored value of the program register block.

Abstract translation: 目的：提供Δ-Σ分配器的结构，以获得合成宽带频率的能力，并通过将Δ-Σ调制器的输出值与外部输入值相加来调整Δ值 吞咽计数器 构成：ΔΣ调制器（41）用于接收频率和外部输入值。 吞咽加法器块（40）用于将外部输入值添加到delta-Σ调制器的输出值。 程序寄存器块（37）用于存储吞咽加法器块的输出值。 脉冲吞咽计数器块（34）由双模预分频器，程序计数器和吞咽计数器形成，以便根据程序寄存器块的存储值对输入频率进行分频。

公开(公告)号：KR1020030013193A

公开(公告)日：2003-02-14

申请号：KR1020010047549

申请日：2001-08-07

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  김남수 ,  윤용식 ,  박필재

IPC: H03D7/00

CPC classification number: H03D7/1441 ,  H03D7/1408 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/1475

Abstract: PURPOSE: A frequency mixer using half local oscillation frequency is provided to remove an offset of a direct current voltage when using a frequency mixer at a homo heterodyne transceiver, and to half a frequency of a local oscillator needed for a high frequency heterodyne transceiver. CONSTITUTION: The first and second input terminals(IN+,IN-) receive high frequency signals as differential signals. The first mixing part(100) comprises the first and second NMOS transistors(M10,M20), which have sources connected to the first input terminal(IN+), drains connected to each other, and gates connected to receive signals(LO+,LO-) from a local oscillator. The second mixing part(200) comprises the third and fourth NMOS transistors(M30,M40), which have sources connected to the second input terminal(IN-), drains connected to each other, and gates connected to receive the signals(LO+,LO-) from the local oscillator.

Abstract translation: 目的：提供使用半本地振荡频率的混频器，以在同频外差收发器使用混频器时消除直流电压的偏移，以及高频外差收发器所需的本地振荡器的一半频率。 构成：第一和第二输入端子（IN +，IN-）接收高频信号作为差分信号。 第一混合部分（100）包括第一和第二NMOS晶体管（M10，M20），其具有连接到第一输入端（IN +）的源极，彼此连接的漏极，以及连接到接收信号（LO +，LO- ）从本地振荡器。 第二混合部分（200）包括具有连接到第二输入端子（IN-）的源极的第三和第四NMOS晶体管（M30，M40），彼此连接的漏极，以及连接以接收信号（LO +， LO-）。

公开(公告)号：KR1020030002416A

公开(公告)日：2003-01-09

申请号：KR1020010038011

申请日：2001-06-29

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  장재홍 ,  김충기 ,  박문양 ,  김성도 ,  윤용식 ,  박필재 ,  김남수 ,  김천수 ,  황남 ,  박정우

IPC: H01L27/04

Abstract: PURPOSE: A multi-metal inductor is provided to reduce a loss of a substrate and minimize a loss of a serial resistance generated from an inductor line by controlling the width of metal wires. CONSTITUTION: The first insulating layer(20) of TEOS/BPSG is formed on a silicon substrate(10). The second insulating layer(40) having a structure of SiO2/SOG/SiO2 is formed on the first insulating layer(20). The first metal wire(30) is formed on the second insulating layer(40). A via-hole(50) is formed on the second insulating layer(40) in order to connect the second metal wire(60) for forming the first metal wire(30) and the inductor. The third insulating layer(80) having the structure of SiO2/SOG/SiO2 is formed on the second insulating layer(40). A plurality of metal layers are formed within the third insulating layer(60). The third metal wire(70) is formed on the second metal wire(60). The third metal wire(70) is protected by a protective layer(90). The third metal wire(70) is connected with the second metal wire(60) through a via hole(51).

Abstract translation: 目的：提供多金属电感以减少基板的损耗，并通过控制金属线的宽度来最小化从电感线产生的串联电阻的损失。 构成：TEOS / BPSG的第一绝缘层（20）形成在硅衬底（10）上。 在第一绝缘层（20）上形成具有SiO 2 / SOG / SiO 2结构的第二绝缘层（40）。 第一金属线（30）形成在第二绝缘层（40）上。 为了连接用于形成第一金属线（30）的第二金属线（60）和电感器，在第二绝缘层（40）上形成通孔（50）。 具有SiO 2 / SOG / SiO 2结构的第三绝缘层（80）形成在第二绝缘层（40）上。 在第三绝缘层（60）内形成多个金属层。 第三金属线（70）形成在第二金属线（60）上。 第三金属线（70）由保护层（90）保护。 第三金属线（70）通过通孔（51）与第二金属线（60）连接。

公开(公告)号：KR100345397B1

公开(公告)日：2002-07-26

申请号：KR1019990062446

申请日：1999-12-27

Applicant: 한국전자통신연구원

Inventor： 한선호 ,  유현규 ,  김충환 ,  김천수 ,  박민

IPC: H03L7/00

Abstract: 본발명은기준신호와비교신호를비교하여위상차신호를생성하는위상비교기와, 위상비교기로부터의위상차신호에기초한펄스성분을포함하는 DC 성분을갖는전압신호를생성하는차지펌프와, 차지펌프로부터공급된전압신호를평활화하여고주파성분이제거된제어전압을생성하는로우패스필터와, 주파수가제어전압의값에대응하는출력신호를출력하는전압제어발진기와, 전압제어발진기로부터생성된출력신호는피드백하는분주회로를구비하는주파수합성기에있어서, 분주회로는복수의상단 T 플립플롭과, 복수의하단 D 플립플롭을구비함으로써, 분주회로에의한지연시간을단축시키는주파수합성기를제공한다.

公开(公告)号：KR1020020035193A

公开(公告)日：2002-05-11

申请号：KR1020000065358

申请日：2000-11-04

Applicant: 한국전자통신연구원

Inventor： 김천수 ,  유현규 ,  황남 ,  박정우

IPC: H01L29/78

CPC classification number: H01L29/7835 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/41766 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A high frequency power device is provided to simplify a fabricating process, by doping impurities to a trench formed in a source region and by filling polysilicon so that an ion implantation process and a high-temperature diffusion process necessitating high energy become unnecessary. CONSTITUTION: A semiconductor layer is of the first conductivity type. A field region of a trench structure is formed in a side of the semiconductor layer. A gate electrode(44) is formed on a predetermined surface of the semiconductor layer. A channel layer(46) of the second conductivity type is laterally diffused from the field region to a width including both sides of the gate electrode and is formed on the semiconductor layer. A source region(47) of the second conductivity type is formed in the channel layer between one side of the gate electrode and the field region. A drain region(48) of the second conductivity type is formed on the semiconductor layer, having a predetermined interval at the other side of the gate electrode. A sinker(37) of the first conductivity type is connected to the semiconductor layer, having a pillar type of a trench structure which penetrates the source region and forms two source regions. A lightly-doped-drain(LDD) region(45) of the second conductivity type is formed on the semiconductor substrate between the drain region and the gate electrode. The first metal electrode is electrically connected to the semiconductor layer through the sinker, in contact with the source regions. The second metal electrode comes in contact with the drain region.

Abstract translation: 目的：提供高频功率器件，以简化制造工艺，通过将杂质掺杂到在源极区域中形成的沟槽并且通过填充多晶硅，使得不需要离子注入工艺和需要高能量的高温扩散工艺。 构成：半导体层是第一导电类型。 沟槽结构的场区形成在半导体层的一侧。 在半导体层的预定表面上形成栅电极（44）。 第二导电类型的沟道层（46）从场区横向扩散到包括栅电极的两侧的宽度，并形成在半导体层上。 在栅电极的一侧和场区之间的沟道层中形成第二导电类型的源极区（47）。 第二导电类型的漏区（48）形成在半导体层上，在栅电极的另一侧具有预定间隔。 第一导电类型的沉降片（37）连接到具有贯穿源极区域并形成两个源极区域的沟槽结构的柱状的半导体层。 在漏区和栅电极之间的半导体衬底上形成第二导电类型的轻掺杂漏极（LDD）区（45）。 第一金属电极通过沉降片与半导体层电连接，与源极区域接触。 第二金属电极与漏极区域接触。

公开(公告)号：KR100296146B1

公开(公告)日：2001-08-07

申请号：KR1019980018711

申请日：1998-05-23

Applicant: 한국전자통신연구원

Inventor： 김충환 ,  김천수 ,  유현규 ,  현영철 ,  박민

IPC: H04B1/62

Abstract: PURPOSE: A small signal linearizing apparatus is provided to improve linearity by feedbacking a nonlinear signal generated from a nonlinear signal generator to an amplifying unit through a feedback unit, amplifying the nonlinear signal to have the opposite phase of the nonlinear component of a small signal amplified through the amplifying unit and canceling the nonlinear component of the amplified small signal. CONSTITUTION: The first and second DC signal cut-off unit(610) are connected to an input terminal(IN). An amplifying unit(630) is connected to the first DC signal cut-off unit(610). The first input signal leakage preventing unit includes one terminal to which a DC bias is applied and the other terminal connected to the input terminal of the amplifying unit(630). A nonlinear signal generating unit is connected in parallel to the amplifying unit(630) and has an input terminal connected to the second DC signal cut-off unit. The second input signal leakage preventing unit(660) includes one terminal to which the DC bias(VGG2) is applied and the other terminal connected to the input terminal of the nonlinear signal generating unit. A load(670) is connected between a power(VDD) and an output terminal(OUT). A feedback unit(680) is connected between the input terminal of the amplifying unit(630) and the output terminal of the nonlinear signal generating unit. A load(690) is connected between the power(VDD) and the output terminal of the nonlinear signal generating unit.

公开(公告)号：KR1020010063876A

公开(公告)日：2001-07-09

申请号：KR1019990061980

申请日：1999-12-24

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  한선호 ,  황종태 ,  조규형

IPC: H03B28/00

Abstract: PURPOSE: A low noise current controlled oscillator having wide band variation characteristic is provided to enable a wide band variation at a low voltage on maintaining a low noise characteristic that an L-C oscillator has the same characteristic by improving the oscillator structure. CONSTITUTION: The first through fourth inductors(L1 to L4) are coupled to a power source(VDD), respectively. The first and second transconductors(M1,M2) are coupled to the first and second inductors(L1,L2), respectively, while the third and fourth transconductors(M3,M4) are coupled to the third and fourth inductors(L3,L4), respectively. The fifth and sixth transconductors(M5,M6) are coupled to the third and fourth inductors(L3,L4) and the first and second transconductors(M1,M2), respectively. The seventh and eighth transconductors(M7,M8) are coupled to the first and second inductors(L1,L2) and the third and fourth transconductors(M3,M4). A main current source adjustment element(VB1) is coupled with between a node of the fifth and sixth transconductors(M5,M6) and a ground and between a node of the seventh and eighth transconductors(M7,M8) and the ground. A subsidiary current source adjustment element(VB2) is coupled with between a node of the first and second transconductors(M1,M2) and the ground and between a node of the third and fourth transconductors(M3,M4) and the ground.

Abstract translation: 目的：提供具有宽带变化特性的低噪声电流控制振荡器，以便通过改善振荡器结构来保持L-C振荡器具有相同特性的低电压宽带变化。 构成：第一至第四电感器（L1至L4）分别耦合到电源（VDD）。 第一和第二跨导体（M1，M2）分别耦合到第一和第二电感器（L1，L2），而第三和第四跨导体（M3，M4）耦合到第三和第四电感器（L3，L4） ， 分别。 第五和第六跨导体（M5，M6）分别耦合到第三和第四电感器（L3，L4）和第一和第二跨导体（M1，M2）。 第七和第八跨导体（M7，M8）耦合到第一和第二电感器（L1，L2）以及第三和第四跨导体（M3，M4）。 主电流源调节元件（VB1）与第五和第六跨导体（M5，M6）的节点和地之间以及第七和第八跨导体（M7，M8）的节点和地之间耦合。 辅助电流源调节元件（VB2）与第一和第二跨导体（M1，M2）的节点和地之间以及第三和第四跨导体（M3，M4）的节点与地之间耦合。

公开(公告)号：KR1020010027910A

公开(公告)日：2001-04-06

申请号：KR1019990039890

申请日：1999-09-16

Applicant: 한국전자통신연구원

Inventor： 김충환 ,  김천수 ,  유현규 ,  박민 ,  김대용

IPC: H03D7/00

Abstract: PURPOSE: A mixer of Gibert cell frequency by using a unipolar switch is provided to reduce loss of gain of converting by supplying the condition of bias optimized by the operation of a unipolar switch. CONSTITUTION: A mixer of Gibert cell frequency by using a unipolar switch includes six FETs(Field Effect Transistors). The radio frequency signal is permitted to the gate of a FET(F311) and the electric current lD1 flows in the drain. The reverse radio frequency signal is permitted to the gate of a FET(F312) and the electric current lD2 flows in the drain. The partial oscillator signal is permitted to the gate of the FET(F313) and the drain of the FET(F313) is connected to the source of the FETs(F311, F312) in common. The radio frequency signal(RF) is permitted to the gate of the FET(F314) and the electric current lD3 flows in the drain connected with the drain of the FET(F311). The reverse radio frequency signal(/RF) is permitted to the gate of the FET(F315) and the electric current lD4 flows in the drain connected with the drain of the FET(F312). The the reverse partial oscillator signal(/LO) is permitted to the gate of the FET(F316) and the drain is connected to the source of the FETs(F314, F315) in common.

Abstract translation: 目的：提供通过使用单极开关的Gibert电池频率的混频器，通过提供通过单极开关的操作优化的偏置条件来减少转换增益的损失。 构成：使用单极开关的Gibert电池频率的混频器包括六个FET（场效应晶体管）。 射频信号被允许到FET的栅极（F311），电流ID1流入漏极。 反向射频信号被允许到FET的栅极（F312），并且电流ID2流入漏极。 部分振荡器信号被允许到FET的栅极（F313），并且FET（F313）的漏极共同连接到FET的源极（F311，F312）。 允许射频信号（RF）到FET（F314）的栅极，并且电流ID3流过与FET（F311）的漏极连接的漏极。 反向射频信号（/ RF）被允许到FET的栅极（F315），并且电流ID4流过与FET的漏极连接的漏极（F312）。 反向部分振荡器信号（/ LO）被允许到FET（F316）的栅极，漏极与FET（F314，F315）的源极共同连接。

公开(公告)号：KR100275541B1

公开(公告)日：2001-01-15

申请号：KR1019970070321

申请日：1997-12-19

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  박민 ,  이상국 ,  남기수

IPC: H01L27/06

Abstract: PURPOSE: A structure of a high frequency resonance circuit for arranging a capacitor in an internal diameter of an inductor and a method for designing the same are provided to reduce an area of a resonance circuit by forming an integrated inductor in an internal diameter of an inductor. CONSTITUTION: An inductor is formed with a metallic line(20) of N layer as an input terminal, metallic lines(22,26) of N-1 layer connected through a contact hole(21) of the input terminal of the metallic layer(20) and a contact hole(25) of a termination of the metallic layer(20), and an inter-metal insulating layer between a lower portion of the metallic line(20) of N layer and an upper portion of the metallic lines(22,26) of N-1 layer. A high frequency resonance circuit is formed with a polysilicon layer(28) of M layer connected with the metallic layer(26) and the contact hole(25), a polysilicon layer(24) of M-1 layer, and an inter-polysilicon insulating layer.

Abstract translation: 目的：提供一种用于布置电感器内径中的电容器的高频谐振电路的结构及其设计方法，以通过在电感器的内径中形成集成电感器来减小谐振电路的面积 。 构成：电感器由N层的金属线（20）形成为输入端子，N-1层的金属线（22,26）通过金属层的输入端子的接触孔（21）连接（ 20）和金属层（20）的端接件的接触孔（25），以及在N层金属线（20）的下部与金属线的上部之间的金属间绝缘层（ 22,26）N-1层。 高频谐振电路形成有与金属层（26）和接触孔（25）连接的M层的多晶硅层（28），M-1层的多晶硅层（24）和多晶硅 绝缘层。

公开(公告)号：KR100249773B1

公开(公告)日：2000-03-15

申请号：KR1019970059873

申请日：1997-11-13

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  구진근 ,  배종욱 ,  현영철 ,  남기수

IPC: H01L21/20

Abstract: 본 발명은 혼합 비정질 박막을 이용한 반도체 제작방법에 관한 것으로서, 반도체 기판 상에 기판 부분의 자연 산화막, 소스와 드레인 영역에서 자연 산화막이 형성되는 단계, 고진공 스퍼터 장비를 이용하여 고온으로 티타늄을 증착하는 단계, 상기 단계에서 자연 산화막과 반응한 Ti-Si 비정질 박막은 남기고 반응하지 않는 티타늄은 선택적으로 식각하는 단계, 상기 단계에서 형성된 비정질 박막위에 고 진공하에서 스퍼터 장비를 이용한 코발트 증착 단계, 상기 증착된 코발트를 급속 열처리 장비를 이용하여 모노 코발트 실리사이드를 형성하는 단계, 상기 측벽 스페이서와 격리 산화막위의 반응하지 않는 코발트를 식각하는 단계, 상기 노출된 코발트 모노 실리사이드를 급속 열처리 장비를 이용하여 코발트 실리사이드를 형성하는 단계를 포함함으로� ��, 반도체 소자 제작 공정시 게이트와 액티브 영역의 노출된 실리콘의 대기와의 노출에 의해 발생한 자연 산화막을 티타늄-실리콘계 비정질상을 이용하여 제거함으로써 코발트 자기 정렬 실리사이드를 형성할 때 액티브 영역에서 정합 성장을 유도할 수 있으며, 이에 따른 전기 저항과 접촉 저항을 낮출 수 있어 소자의 지연 속도와 안정성을 향상시키는 효과가 있다.