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公开(公告)号：KR101155886B1
公开(公告)日：2012-07-13
申请号：KR1020110040708
申请日：2011-04-29
CPC classification number: H04B1/0475 , H04B1/0483 , H04B2001/0491
Abstract: PURPOSE: An up-converting digital-RF transmitter using scrambler is provided to increase the whole linearity index of a transmitter system. CONSTITUTION: Decoding units(33,34) convert a digital signal into a signal of unit-weighted-code in a binary-code type. Scrambling units(35,36) scramble an order of converted output signals. A plurality of digital RF(Radio Frequency) converting cells is connected to the multiple-bit output signals of the scrambling unit. A differential RF signal is generated by mixing a differential carrier signal and a control signal. A local oscillator or a frequency synthesizer(61) generate the differential carrier signal.
Abstract translation: 目的：提供使用扰频器的上转换数字RF发射器，以增加发射机系统的整体线性度。 构成：解码单元（33,34）将数字信号转换为二进制码类型的单位加权码的信号。 加扰单元（35,36）对转换后的输出信号进行加扰。 多个数字RF（射频）转换单元连接到加扰单元的多位输出信号。 通过混合差分载波信号和控制信号来产生差分RF信号。 本地振荡器或频率合成器（61）产生差分载波信号。
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公开(公告)号：KR1020120072247A
公开(公告)日：2012-07-03
申请号：KR1020100134084
申请日：2010-12-23
Applicant: 한국전자통신연구원
IPC: H03L7/085
CPC classification number: H03L7/0891 , H03D13/004 , H03L7/097
Abstract: PURPOSE: A frequency comparator is provided to form a simple hardware structure by using a shift register in a frequency comparator applied to an adaptive frequency calibration loop of a PLP(phase-locked loop). CONSTITUTION: An input unit(230) generates a first reference signal and a second reference signal having differential relation and a 180 degree phase difference of 50% of a duty ratio over a reference signal divided from a reference frequency demultiplier. An up shift register(240) and a down shift register(250) respectively connect a first reference signal and a second reference signal to each reset terminal. An input terminal of the up shift register and the down shift register receives a logic high signal. An output unit(260) outputs a comparison value by comparing a first lower output bit in the up shift register and a second lower output bit in the down shift register.
Abstract translation: 目的：提供频率比较器以通过使用施加到PLP（锁相环）的自适应频率校准环路的频率比较器中的移位寄存器来形成简单的硬件结构。 构成：输入单元（230）产生具有差分关系的第一参考信号和第二参考信号以及占空比的50％相对于从参考分频器分频的参考信号的180度相位差。 上移位寄存器（240）和下移寄存器（250）分别将第一参考信号和第二参考信号连接到每个复位端。 上移寄存器和下移寄存器的输入端接收逻辑高电平信号。 输出单元（260）通过比较上移寄存器中的第一较低输出位和下移寄存器中的第二较低输出位来输出比较值。
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公开(公告)号：KR1020120066307A
公开(公告)日：2012-06-22
申请号：KR1020100127576
申请日：2010-12-14
Applicant: 한국전자통신연구원
IPC: G01S13/02
CPC classification number: G01S7/2921 , H03M1/1215 , H03M1/1265 , G01S13/02
Abstract: PURPOSE: A time-interleaving type pulse-signal recovering device is provided to reduce a time to restore a pulse signal received from a receiver. CONSTITUTION: A time-interleaving type pulse-signal recovering device comprises a plurality of sampling blocks, a sampling clock generator, and a multiplexer(120). The sampling block comprises buffer arrays(100_1-100_N). The buffer array generates a plurality of signals by using a sampling period. A plurality of the sampling blocks comprises a track and hold unit. The track and hold unit senses the level of a received pulse signal. The multiplexer inputs the output signal of the track and hold unit and outputs one input signal from a plurality of input signals.
Abstract translation: 目的：提供时间交织型脉冲信号恢复装置，以减少恢复从接收机接收的脉冲信号的时间。 构成：时间交织型脉冲信号恢复装置包括多个采样块，采样时钟发生器和多路复用器（120）。 采样块包括缓冲器阵列（100_1-100_N）。 缓冲器阵列通过采样周期产生多个信号。 多个采样块包括轨道和保持单元。 轨道和保持单元感测接收到的脉冲信号的电平。 多路复用器输入轨道和保持单元的输出信号，并从多个输入信号输出一个输入信号。
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公开(公告)号：KR1020110068601A
公开(公告)日：2011-06-22
申请号：KR1020090125632
申请日：2009-12-16
Applicant: 한국전자통신연구원
IPC: H03H17/02
CPC classification number: H03H17/02 , H03H17/0657 , H03H17/0664 , H03H17/0671
Abstract: PURPOSE: A second order sinc decimation filter is provided to reuse a clock signal for controlling an input unit of a signal transmitting channel, thereby drastically simplifying a switching circuit. CONSTITUTION: A second order sinc decimation filter includes six signal transmitting channels(511~516) and two signal output channels. The signal transmitting channels are connected between input node A and middle node B. The signal output channels are connected between middle node B and output node C. The signal transmitting channels and the signal output channels can configure a signal transmitting unit and an adding unit of the second order sinc decimation filter. A discrete signal can be applied to input node A. The discrete signal is generated by sampling a current signal outputted from a transconductor. A second order decimation circuit operates according to a clock signal with signal timing.
Abstract translation: 目的：提供二阶sinc抽取滤波器以重新使用时钟信号来控制信号传输通道的输入单元，从而大大简化了开关电路。 构成：二阶sinc抽取滤波器包括六个信号发送通道（511〜516）和两个信号输出通道。 信号发送通道连接在输入节点A和中间节点B之间。信号输出通道连接在中间节点B和输出节点C之间。信号发送通道和信号输出通道可以配置信号发送单元和加法单元 二阶sinc抽取滤波器。 离散信号可以被施加到输入节点A.离散信号通过对从跨导体输出的电流信号进行采样而产生。 二阶抽选电路根据具有信号定时的时钟信号进行操作。
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公开(公告)号：KR1020100117339A
公开(公告)日：2010-11-03
申请号：KR1020090036029
申请日：2009-04-24
Applicant: 한국전자통신연구원
CPC classification number: H03L7/16 , H03L7/095 , H03L7/099 , H03L7/103 , H03L2207/50
Abstract: PURPOSE: A digital lock detection apparatus and a frequency synthesizer having the same are provided to detect the lock state in the digital PLL by using a simple delay circuit and a comparator circuit. CONSTITUTION: A comparison unit(210) is inputted with a plurality of control bits. The comparator outputs a bit signal including the bit information on the locking state of the control bits. A delay cell block(220) outputs one clock signal by combining one bit signal outputted from the comparator and a signal which is made by delaying the bit signal as much as the predetermined time.
Abstract translation: 目的：提供一种数字锁定检测装置和具有该锁定检测装置的频率合成器，以通过使用简单的延迟电路和比较器电路来检测数字PLL中的锁定状态。 构成：比较单元（210）输入多个控制位。 比较器输出包括关于控制位的锁定状态的位信息的位信号。 延迟单元块（220）通过组合从比较器输出的一位信号和通过将比特信号延迟多达预定时间而产生的信号来输出一个时钟信号。
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Patent Agency Ranking
公开(公告)号：KR1020100066320A
公开(公告)日：2010-06-17
申请号：KR1020090060619
申请日：2009-07-03
Applicant: 한국전자통신연구원
CPC classification number: H03H17/08 , H03H21/00 , H03H21/0012 , H03L7/093 , H03L7/0992
Abstract: PURPOSE: A digital proportional integral loop filter is provided to improve the stability of all digital phase locked loop using a proportional integral loop filter. CONSTITUTION: A first proportion amplifier(210) multiplies a first proportion loop gain and a phase-error value. A first integral amplifier(220) multiplies a phase error accumulated value and a first integral loop gain. A second proportion amplifier(240) multiplies the phase-error value and a second proportion loop. A second integral amplifier(250) multiplies the phase-error accumulated value and a second integral loop gain. The first offset generating unit(260) generates a first offset. A second offset generating unit(270) generates a second offset. A first adder(230) adds the outputs of the first proportion amplifier and the first integral amplifier. A second adder(280) adds the outputs of the second proportion amplifier, the second integral amplifier, the first offset generating unit, and the second offset generating unit.
Abstract translation: 目的：提供数字比例积分环路滤波器，以使用比例积分环路滤波器来提高所有数字锁相环的稳定性。 构成：第一比例放大器（210）将第一比例环增益和相位误差值相乘。 第一积分放大器（220）将相位误差累加值和第一积分环路增益相乘。 第二比例放大器（240）将相位误差值和第二比例循环相乘。 第二积分放大器（250）将相位误差累积值和第二积分环路增益相乘。 第一偏移生成单元（260）生成第一偏移。 第二偏移生成单元（270）产生第二偏移。 第一加法器（230）将第一比例放大器和第一积分放大器的输出相加。 第二加法器（280）将第二比例放大器，第二积分放大器，第一偏移生成单元和第二偏移生成单元的输出相加。
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公开(公告)号：KR1020100064285A
公开(公告)日：2010-06-14
申请号：KR1020090027316
申请日：2009-03-31
Applicant: 한국전자통신연구원
Abstract: PURPOSE: An interfering signal controlling apparatus and an interfering signal controlling method using a selective frequency phase converter are provided to effectively eliminate the interfering signal not only narrow frequency band but wide frequency band using a differential amplification principle. CONSTITUTION: A first phase converter(20) differential-outputs a first and a second signals including a phase difference of 180 angle by changing the phase of received RF signal. A second phase converter(21) changes selectively the phase of the signal of a specific frequency band as a specific size in the first signal. A third phase converter(22) changes selectively the phase of the signal of the specific frequency band as the specific size in the second signal. An adder(50) adds the output of the second phase converter and the output of the third phase converter. The specific frequency band signal of the second phase converter and the specific frequency band signal of the third phase converter not have a phase difference of 180 angle.
Abstract translation: 目的：提供一种使用选择性频率相位转换器的干扰信号控制装置和干扰信号控制方法，以便利用差分放大原理，有效地消除干扰信号不仅具有窄频带宽宽频带。 构成：通过改变接收的RF信号的相位，第一相位转换器（20）差分输出包括180°相位差的第一和第二信号。 第二相位转换器（21）选择性地改变特定频带的信号的相位作为第一信号中的特定尺寸。 第三相位转换器（22）选择性地改变特定频带的信号的相位作为第二信号中的特定尺寸。 加法器（50）将第二相位转换器的输出和第三相位转换器的输出相加。 第二相转换器的特定频带信号和第三相转换器的特定频带信号不具有180°的相位差。
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公开(公告)号：KR1020100062740A
公开(公告)日：2010-06-10
申请号：KR1020080121509
申请日：2008-12-02
Applicant: 한국전자통신연구원
IPC: H03F3/45
CPC classification number: H03F3/45183 , H03F3/45475 , H03F2203/45138
Abstract: PURPOSE: An operation transconductance amplifier for a filter designing of a vhf bandwidth is provided to gain an OTA property by using a base unit conversion cell of fewer comparing with existing Nauta OTA circuit structure. CONSTITUTION: A first and a second parallel inverters(21,22) are respectively inputted a first and a second input voltage through an input terminal. The input terminal and an output terminal of a first intersection feedback inverter(23) are respectively connected to the output terminal of the second parallel conversion cell and the output terminal of the first parallel conversion cell. The input terminal and the output terminal of a second intersection feedback inverter(24) are respectively connected to the output terminal of the first parallel conversion cell and the output terminal of the second parallel conversion cell. A transconductance and an outputting admittance of the first parallel inverter and the second parallel inverter are similar each other. The transconductance and the outputting admittance of the first intersection feedback inverter and the second intersection feedback inverter are similar each other.
Abstract translation: 目的：提供用于设计vhf带宽的滤波器的运算跨导放大器，通过使用与现有Nauta OTA电路结构相比较少的基本单元转换单元来获得OTA属性。 构成：第一和第二并联逆变器（21,22）分别通过输入端子输入第一和第二输入电压。 第一交叉反馈反相器（23）的输入端子和输出端子分别连接到第二并联变换单元的输出端子和第一并联变换单元的输出端子。 第二交叉反馈反相器（24）的输入端子和输出端子分别连接到第一并联变换单元的输出端子和第二并联变换单元的输出端子。 第一并联逆变器和第二并联逆变器的跨导和输出导纳彼此相似。 第一交叉反馈逆变器和第二交叉反馈逆变器的跨导和输出导纳彼此相似。
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公开(公告)号：KR1020090060896A
公开(公告)日：2009-06-15
申请号：KR1020070127879
申请日：2007-12-10
Applicant: 한국전자통신연구원
IPC: H01L27/14 , H01L29/737
CPC classification number: H01L27/14643 , G01S7/4863 , G01S17/89 , H01L27/14681 , H04N5/369
Abstract: A photo detector array in which a readout IC is integrated for a laser image signal and a manufacturing method thereof are provided to simplify a manufacturing process by excluding a hybrid packaging process of a separate flip chip. A plurality of optical detection pixels(210) includes a photo diode and a first heterojunction bipolar transistor. The photo diode converts incident light energy into electrical energy. The first heterojunction bipolar transistor selectively converts the electrical energy of the photo diode into electrical signals. An output control circuit(220) includes a second heterojunction bipolar transistor which controls an output of the electrical signals transmitted from a plurality of optical detection pixels. The photo diode, the first heterojunction bipolar transistor, and the second heterojunction bipolar transistor are formed into a single chip integration type on a semi-insulation InP substrate.
Abstract translation: 提供了其中集成了用于激光图像信号的读出IC的光电检测器阵列及其制造方法，以通过排除单独倒装芯片的混合封装处理来简化制造过程。 多个光学检测像素（210）包括光电二极管和第一异质结双极晶体管。 光电二极管将入射光能转换为电能。 第一异质结双极晶体管选择性地将光电二极管的电能转换为电信号。 输出控制电路（220）包括第二异质结双极晶体管，其控制从多个光学检测像素发送的电信号的输出。 光电二极管，第一异质结双极晶体管和第二异质结双极晶体管在半绝缘InP衬底上形成为单芯片积分型。
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公开(公告)号：KR100849926B1
公开(公告)日：2008-08-04
申请号：KR1020070021795
申请日：2007-03-06
Applicant: 한국전자통신연구원
IPC: H01L29/778
Abstract: 본 발명은 티형 게이트 전극을 갖는 부정형 고 전자 이동도 트랜지스터 제조 방법에 관한 것으로서, 에피 성장층이 성장된 기판 상에 소스 및 드레인 전극을 형성하는 단계; 상기 소스 및 드레인 전극이 형성된 상기 기판 전면에 보호막을 형성하는 단계; 상기 보호막 상에 제1 감광막을 형성한 후, 마스크 패턴을 이용하여 상기 기판의 상부가 노출되도록 상기 제1 감광막과 상기 보호막을 패터닝하는 단계; 상기 보호막 상에 남아있는 상기 제1 감광막을 제거한 후, 상기 기판 전면에 상기 보호막 패턴 폭보다 적은 미세 패턴을 갖는 제2 감광막을 형성하는 단계; 상기 미세 패턴을 이용하여 상기 남겨진 보호막을 식각한 후, 상기 제2 감광막을 제거하는 단계; 상기 기판 전면에 다층 구조의 제3 감광막을 형성한 후, 티자 형태의 게이트 전극이 형성되도록 상기 제3 감광막을 패터닝하는 단계; 상기 미세 패턴으로 식각된 상기 보호막을 통해 상기 기판의 상부를 식각하여 상기 기판 상면에 리세스를 형성하는 단계; 및 상기 리세스가 형성된 상기 기판 전면에 게이트 전극용 금속을 증착한 후, 상기 제3 감광막 및 상기 게이트 전극용 금속을 제거하여 상기 리세스를 통해 상기 기판과 연결되는 티자형 게이트 전극을 형성하는 단계를 포함한다. 이에 따라, 게이트 전극의 안정성을 향상시키고 소자의 활성영역을 보호하며, 티형 게이트의 다리 영역에만 보호막이 남게 하여 기생 캐패시턴스를 감소시킬 수 있다. 또한, 게이트 리세스 식각시 건식 식각 방법을 이용함으로써, 게이트 미세 선폭을 유지하고, 소스 저항을 감소시키고, 게이트-소스 및 게이트-드레인 캐패시턴스를 감소시켜 고주파 특성을 향상시킬 수 있다.
부정형 고 전자 이동도 트랜지스터, 티형 게이트, 리세스 식각, 실리콘 질화막, 반응성 이온 식각, 유도 결합 플라즈마
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