公开(公告)号：EP0858859A1

公开(公告)日：1998-08-19

申请号：EP97925301.0

申请日：1997-06-06

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： SAKAI, Yoshinori ,  SUETSUGU, Kenichiro ,  YAMAGUCHI, Atsushi

IPC: B23K35/26

CPC classification number: B23K35/262 ,  B23K2201/36 ,  H05K3/3442 ,  H05K3/3463 ,  H05K2201/10909

Abstract: A lead-free solder alloy of electrode for joining electronic parts fine in texture and excellent in thermal fatigue resistant characteristic is presented.
This is a solder alloy of electrode for joining electronic parts comprising Sn, Ag and Cu as principal components, and more particularly a solder alloy of electrode for joining electronic parts containing 92 to 97 wt.% of Sn, 3.0 to 6.0 wt. % of Ag, and 0.1 to 2.0 wt. % of Cu. By adding a small amount of Ag to the solder mainly composed of Sn, a fine alloy texture is formed, and texture changes are decreased, so that an alloy excellent in thermal fatigue resistance is obtained. Further, by adding a small amount of Cu, an intermetallic compound is formed, and the junction strength is improved.

Abstract translation: 提出了一种无电极焊接合金，用于连接电子零件质地细腻，耐热疲劳特性优异的电极。 这是用于连接包含Sn，Ag和Cu的电子部件作为主要成分的电极用焊料合金，特别是用于接合含有92〜97重量％的Sn，3.0〜6.0重量％的电子部件的电极用焊料合金。 Ag％，0.1〜2.0wt。 Cu的百分比。 通过向主要由Sn组成的焊料中添加少量Ag，形成微细的合金织构，并且纹理变化减小，从而获得耐热疲劳性优异的合金。 此外，通过添加少量的Cu，形成金属间化合物，结合强度提高。

公开(公告)号：EP0797266A3

公开(公告)日：1998-07-22

申请号：EP97301813

申请日：1997-03-18

Applicant: NGK SPARK PLUG CO

Inventor： ITO KENJI

IPC: H01P1/205 ,  H01P7/04 ,  H01P11/00 ,  H05K1/02 ,  H05K3/28 ,  H05K3/34

CPC classification number: H01P11/007 ,  H01P1/2056 ,  H05K1/0243 ,  H05K3/282 ,  H05K3/3442 ,  H05K2201/09036 ,  H05K2201/09072 ,  H05K2201/1006 ,  H05K2201/10909 ,  H05K2201/10969 ,  Y02P70/613

Abstract: In a dielectric filter to be mounted on a printed circuit board, a conductive layer (x) formed on the surface of a dielectric substrate (1) includes an electroless copper-plated layer (m) formed on the surface of the substrate, and a conductive covering layer (n) having good dielectric conductivity and good solder wettability and formed on the surface of the electroless copper-plated layer (m). In place of the conductive covering layer (n) or in addition to the conductive covering layer (n), there is provided a protective synthetic resin layer (p) which covers the electroless copper-plated layer (m) or the conductive covering layer (n) and which vanishes upon exposure to heat of molten solder (25). Even when the conductive layer (x) is formed by electroless copper-plating, the conductive layer (x) is free from stain. Moreover, a terminal portion of the conductive layer (x) formed on the surface of the dielectric filter (1) can be soldered to a conductive path formed on a printed circuit board to thereby establish electric connection therebetween.

公开(公告)号：EP0792463A4

公开(公告)日：1998-06-24

申请号：EP95940718

申请日：1995-11-15

Applicant: FORMFACTOR INC

Inventor： KHANDROS IGOR Y ,  MATHIEU GAETAN L ,  ELDRIDGE BENJAMIN N ,  GRUBE GARY W

IPC: G01R1/06 ,  B23K1/00 ,  B23K20/00 ,  B32B15/08 ,  C23C18/16 ,  C25D5/08 ,  C25D5/22 ,  C25D7/12 ,  C25D21/02 ,  G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R31/26 ,  G01R31/28 ,  H01L21/00 ,  H01L21/02 ,  H01L21/288 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L21/603 ,  H01L21/66 ,  H01L23/48 ,  H01L23/485 ,  H01L23/49 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16 ,  H01R12/52 ,  H05K1/14 ,  H05K3/20 ,  H05K3/30 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40 ,  H05K7/10

CPC classification number: H05K7/1069 ,  B23K1/0016 ,  B23K20/004 ,  B23K2201/40 ,  C25D5/08 ,  C25D5/22 ,  C25D7/12 ,  C25D21/02 ,  G01R1/0483 ,  G01R31/2863 ,  H01L21/288 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/67138 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16145 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45644 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/48844 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4015 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2224/48744 ,  H01L2924/20751 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/00015 ,  H01L2924/2075 ,  H01L2924/20754

Abstract: Resilient contact structures (430) are mounted directly to bond pads (410) on semiconductor dies (402a, 402b), prior to the dies (402a, 402b) being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies (402a, 402b) to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies (702, 704) with a circuit board (710) or the like having a plurality of terminals (712) disposed on a surface thereof. Subsequently, the semiconductor dies (402a, 402b) may be singulated from the semiconductor wafer, whereupon the same resilient contact structures (430) can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements (430) of the present invention as the resilient contact structures, burn-in (792) can be performed at temperatures of at least 150 °C, and can be completed in less than 60 minutes.

Abstract translation: 本发明提供一种在从半导体晶片分离之前测试半导体器件（702,704）的方法。 所述方法包括以下步骤：将驻留在半导体晶片上的至少一个半导体器件（702,704）上的多个弹性接触结构（708）直接固定到多个第一端子上，每个所述弹性接触结构 具有尖端并从半导体器件的表面延伸; 将具有多个第二端子（712）的衬底（710）推向半导体器件的表面以实现弹性接触结构的相应的第二端子和尖端之间的多个电连接; 并向衬底的第二端提供信号以锻炼半导体器件。

公开(公告)号：EP0117111B1

公开(公告)日：1991-05-08

申请号：EP84300895.4

申请日：1984-02-13

Applicant: FUJITSU LIMITED

Inventor： Sugimoto, Masahiro ,  Wakabayashi, Tetsushi ,  Muratake, Kiyoshi Musashinakahara Royaruparesu

IPC: H01L23/49 ,  H01L23/055 ,  H05K3/32 ,  H01L23/532

CPC classification number: H01L24/32 ,  H01L23/057 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/351 ,  H05K3/3426 ,  H05K2201/10704 ,  H05K2201/10909 ,  H05K2201/2081 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00

公开(公告)号：EP0297511A3

公开(公告)日：1991-03-13

申请号：EP88110305.5

申请日：1988-06-28

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LIMITED

Inventor： Sasame, Akira c/o Itami Works of Sumitomo ,  Sakanoue, Hitoyuki c/o Itami works of Sumitomo ,  Tekeuchi, Hisao c/o Itami works of Sumitomo ,  Miyake, Masaya c/o Itami works of Sumitomo ,  Yamakawa, Akira c/o Itami works of Sumitomo ,  Yushio, Yasuhisa c/o Itami works of Sumitomo ,  Akazawa, Hitoshi c/o Itami works of Sumitomo

IPC: H01L23/50 ,  H01L21/48 ,  H01L23/14 ,  H01L23/08 ,  H01L23/10

CPC classification number: H05K3/3405 ,  H01L21/4853 ,  H01L23/10 ,  H01L23/49582 ,  H01L23/49811 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12033 ,  H01L2924/12042 ,  H05K1/0306 ,  H05K3/246 ,  H05K3/3421 ,  H05K2201/0347 ,  H05K2201/1025 ,  H05K2201/1034 ,  H05K2201/10909 ,  H05K2201/10916 ,  Y10T428/12576 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A connection structure between lead frames (3) and a base plate (1) of aluminum nitride, to be applied as a connection structure between components of a semiconductor apparatus, comprises the base plate formed of a sintered body of aluminum nitride on which a semiconductor device is to be mounted, the lead frames including, as a main material, iron alloy containing nickel in 29 wt.% and cobalt in 17 wt.%, and silver solder (9) for joining the base plate and the lead frames. A surface of the lead frame to be joined to the base plate is formed of oxygen-free copper of a high plastic deformativity to relieve, by plastic deformation of itself, a thermal stress caused by a difference between a thermal expansion coefficient of the base plate and that of the lead frame in a cooling process at the time of soldering. Preferably, only a portion of each lead frame (3) to be joined to the base plate comprises an inner layer portion of iron alloy containing nickel in 29 wt.% and cobalt in 17 wt.%, and an outer layer portion of oxygen-free copper.

公开(公告)号：EP0364479A1

公开(公告)日：1990-04-25

申请号：EP88905490.0

申请日：1988-05-16

Applicant: CRAY RESEARCH, INC.

Inventor： CRAY, Seymour, R. ,  KRAJEWSKY, Nicholas, J.

IPC: H01L21 ,  H01L23 ,  H01R12 ,  H05K3

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/4943 ,  H01L2224/78301 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12033 ,  H01L2924/14 ,  H01R12/523 ,  H05K3/308 ,  H05K3/328 ,  H05K3/368 ,  H05K2201/096 ,  H05K2201/1059 ,  H05K2201/10825 ,  H05K2201/10909 ,  H05K2201/10946 ,  H05K2203/0495 ,  Y10T29/49135 ,  Y10T29/4914 ,  Y10T29/49153 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/48

Abstract: Procédé et dispositif d'interconnexion de circuits électroniques (104) utilisant de l'or recuit complet presque pur qui est comprimé mécaniquement à l'intérieur de trous traversants dorés (111). Cette invention permet de fixer des dés de circuits intégrés (104) directement sur les cartes de circuit (110) en soudant des fils en or en forme de perles (101) sur les blocs de soudage (105) des dés de circuits intégrés (104) de manière essentiellement perpendiculaire aux surfaces des dés (104) et en introduisant les conducteurs en or (101) dans les trous traversants dorés (111) des cartes de circuit (110) qui assurent une connexion mécanique et électrique une fois que les conducteurs (101) sont comprimés dans les trous traversants dorés (111). La présente invention s'applique également lors de l'interconnexion d'assemblages de cartes de circuit en sandwich (200), où des fils conducteurs en or mou sont introduits dans des trous traversants dorés alignés axialement dans les cartes de circuits (212, 214, 216, 217, 219, 221) et comprimés de sorte que lesdits fils conducteurs en or se déforment à l'intérieur des trous traversants dorés, établissant ainsi un contact électrique entre les cartes de circuits (212, 214, 216, 217, 219, 221).

公开(公告)号：EP0100175A3

公开(公告)日：1986-02-05

申请号：EP83304018

申请日：1983-07-11

Applicant: Corning Glass Works

Inventor： Womack, Billy Bob

IPC: H01G01/147

CPC classification number: H01G4/2325 ,  H05K3/3442 ,  H05K2201/10636 ,  H05K2201/10909 ,  Y02P70/611 ,  Y02P70/613

Abstract: A monolithic capacitor chip (10') comprises a body formed of stacked, alternately arranged layers of dielectric material (16) and metallic electrode material (18'), altemate electrodes extending to opposite end faces of the body, and a noncompliant metalized layer (20', 22') on each of the opposite end faces electrically contacting the electrodes (18') extending thereto. Each of the noncompliant metalized layers (20', 22) is provided with a compliant coating (32,34) of an alloy preferably comprising more than 90 % lead. A metallic layer (36, 38) is disposed over the surface of each of the compliant coatings (32, 34), the melting point of the metallic layers (36, 38) being greater than that of the compliant coating (32, 34). The metallic layer (36, 38) preferably consists of a layer of copper or nickel plating, the surface of which is plated with an oxidation resistant metal such as tin, gold, or the like.

公开(公告)号：EP0117111A2

公开(公告)日：1984-08-29

申请号：EP84300895.4

申请日：1984-02-13

Applicant: FUJITSU LIMITED

Inventor： Sugimoto, Masahiro ,  Wakabayashi, Tetsushi ,  Muratake, Kiyoshi Musashinakahara Royaruparesu

IPC: H01L23/49 ,  H01L23/055 ,  H05K3/32 ,  H01L23/532

CPC classification number: H01L24/32 ,  H01L23/057 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/351 ,  H05K3/3426 ,  H05K2201/10704 ,  H05K2201/10909 ,  H05K2201/2081 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A semiconductor device for mounting directly on a circuit board comprises a semiconductor chip 5, a package 1,7,8 in which the semiconductor chip 5 is mounted, a plurality of conductor pads 3 provided on the outer surface of the package 1,7,8 and a plurality of conductor pins 40, fixed to the conductor pads and projecting substantially normally away from them. The conductor pins 40 are fixed to contact pads 9 on a circuit board 2 and electrically and mechanically interconnect the package 1, 7, 8 and the circuit board 2. The pins 40 accommodate the differing thermal expansion of the package 1, 7, 8 and the circuit board 2.

公开(公告)号：WO2016134804A1

公开(公告)日：2016-09-01

申请号：PCT/EP2015/080853

申请日：2015-12-21

Applicant: EPCOS AG

Inventor： KOINI, Markus ,  KONRAD, Jürgen ,  RINNER, Franz ,  PUFF, Markus ,  STADLOBER, Monika ,  KÜGERL, Georg ,  WIPPEL, Thomas

IPC: H01G4/232 ,  H01G4/38 ,  H01G2/06 ,  H05K1/18

CPC classification number: H01G4/228 ,  H01G2/06 ,  H01G4/232 ,  H01G4/2325 ,  H01G4/30 ,  H01G4/38 ,  H05K1/181 ,  H05K3/3426 ,  H05K2201/10015 ,  H05K2201/10757 ,  H05K2201/10818 ,  H05K2201/10909 ,  Y02P70/613

Abstract: Es wird ein elektrisches Bauelement (1) angeben, das mehrere Teilkörper (2), einen Sockel (3), auf dem die Teilkörper (2) angeordnet sind, und wenigstens einen Anschlusskontakt (4, 5) zum elektrischen Anschluss der Teilkörper (2) an einem Träger (13) aufweist. Weiterhin wird ein Verfahren zur Herstellung eines elektrischen Bauelements (1) aufweisend ein oder mehrere Teilkörper (2) angegeben.

Abstract translation: 它是指定的电子组件（1），所述多个子体（2），基座（3）在其上部分本体（2）被布置，并且至少一个端子触头（4，5），用于局部机构的电连接（2） 在载体（13）。 此外，用于制造电气部件（1）的方法，提供了包含一个或多个部分主体（2）。

公开(公告)号：WO2013094922A1

公开(公告)日：2013-06-27

申请号：PCT/KR2012/010789

申请日：2012-12-12

Applicant: LG INNOTEK CO., LTD.

Inventor： LIM, Seol Hee ,  JO, Yun Kyoung ,  KIM, Ae Rim ,  EOM, Sai Ran ,  PARK, Chang Hwa

IPC: H05K1/02 ,  G06K19/07

CPC classification number: H05K3/301 ,  C23C18/1653 ,  C25D3/12 ,  C25D3/16 ,  C25D3/48 ,  C25D3/50 ,  C25D3/562 ,  C25D3/567 ,  C25D3/62 ,  C25D5/12 ,  H05K1/092 ,  H05K1/117 ,  H05K1/18 ,  H05K3/185 ,  H05K3/244 ,  H05K2201/10159 ,  H05K2201/10909 ,  H05K2203/049 ,  H05K2203/1572 ,  Y10T29/49128

Abstract: Provided is a printed circuit board for a memory card, including: an insulating layer; a mounting unit which is formed on a first surface of the insulating layer and is electrically connected to a memory device; and a terminal unit which is formed on a second surface of the insulating layer and is electrically connected to electronic apparatuses of an outside, wherein the mounting unit and the terminal unit are formed of metal layers composed of the same materials as each other.

Abstract translation: 提供一种用于存储卡的印刷电路板，包括：绝缘层; 安装单元，其形成在所述绝缘层的第一表面上并电连接到存储器件; 以及端子单元，其形成在所述绝缘层的第二表面上并且电连接到外部的电子设备，其中所述安装单元和所述端子单元由彼此相同的材料构成的金属层形成。