公开(公告)号：EP2235743A4

公开(公告)日：2013-03-20

申请号：EP09704665

申请日：2009-01-15

Applicant: IBM

Inventor： DALTON TIMOTHY ,  DORIS BRUCE B ,  KIM HO-CHEOL ,  RADENS CARL

IPC: H01L21/033 ,  B81C1/00

CPC classification number: H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/0338 ,  Y10T428/24612

公开(公告)号：EP1974372A4

公开(公告)日：2009-12-09

申请号：EP07716303

申请日：2007-01-03

Applicant: IBM

Inventor： CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WANG YUN Y ,  KWONG HON WONG KEITH

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1779436A4

公开(公告)日：2009-05-13

申请号：EP05790060

申请日：2005-06-20

Applicant: IBM

Inventor： DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

IPC: H01L27/01 ,  H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76

CPC classification number: H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

Abstract: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

公开(公告)号：EP1683187A4

公开(公告)日：2008-08-27

申请号：EP04810633

申请日：2004-11-09

Applicant: IBM

Inventor： DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

公开(公告)号：EP1678753A4

公开(公告)日：2008-08-20

申请号：EP04795234

申请日：2004-10-15

Applicant: IBM

Inventor： DORIS BRUCE B ,  GLUSCHENKOV OLEG G

IPC: H01L21/76 ,  H01L20060101 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7846

Abstract: A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si-SiO2 interfaces in a direction parallel to the direction of current flow and in a direction transverse to current flow. The device and method also provide a p-channel field effect transistor (pFET) having a shallow trench isolation with an overhang that overhangs Si-SiO2 interfaces in a direction transverse to current flow. However, the shallow trench isolation for the pFET is devoid of overhangs, in the direction parallel to the direction of current flow.

公开(公告)号：EP1692717A4

公开(公告)日：2008-04-09

申请号：EP03819249

申请日：2003-12-08

Applicant: IBM

Inventor： BUEHRER FREDERICK WILLIAM ,  CHIDAMBARRAO DURESETI ,  DORIS BRUCE B ,  HUANG HSIANG-JEN ,  YANG HAINING

IPC: H01L21/336 ,  H01L21/22 ,  H01L21/265 ,  H01L21/324 ,  H01L21/425 ,  H01L21/8238 ,  H01L27/01 ,  H01L29/10 ,  H01L29/167 ,  H01L29/76

CPC classification number: H01L29/7842 ,  H01L21/22 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer ) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations and/or profiles/gradients. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.

Abstract translation: 施加在由半导体材料的结构或主体（例如衬底或层）限定的边界上的应力膜提供了在接近边界的半导体材料中从拉应力至压应力的变化，并且用于修改退火期间的硼扩散速率和 从而改变最终的硼浓度和/或分布/梯度。 在场效应晶体管的情况下，栅极结构可以形成为具有或不具有侧壁以相对于源极/漏极，延伸和/或晕圈注入来调节边界的位置。 可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。 可以通过相同的工艺步骤同时实现nFET和pFET的结电容的降低。

公开(公告)号：JP2011101002A

公开(公告)日：2011-05-19

申请号：JP2010238380

申请日：2010-10-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  FALTERMEIER JONATHAN E ,  BASKER VEERARAGHAVAN S ,  DORIS BRUCE B

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/26586 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a reliable process for achieving selectivity for selectively etching spacer/side wall material on fin against spacer/side wall material on a gate stack of finFET structure in an integrated circuit. SOLUTION: A spacer material is deposited in conformal manner on both fin and gate stack. Inclined impurity injection is performed almost parallel to the gate stack so that only the spacer material deposited on the fin is selectively damaged. Thus, such finFET is provided as covers a part of fin of the semiconductor material formed on a substrate and contains a spacer having substantially uniform profile along the length of the gate stack. By a damage caused by inclined injection, the spacer material on the fin can be so etched as has a higher selectivity than the spacer material on the gate stack. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种可靠的方法，用于实现在集成电路中在finFET结构的栅叠层上选择性地蚀刻翅片上的间隔件/侧壁材料的隔离物/侧壁材料的选择性。 解决方案：隔板材料以共形方式沉积在散热片和栅极叠层上。 倾斜的杂质注入与栅极堆叠几乎平行地进行，使得仅沉积在鳍上的间隔物被选择性地损坏。 因此，这种finFET被设置为覆盖形成在衬底上的半导体材料的鳍片的一部分，并且包含沿着栅极堆叠的长度具有基本均匀轮廓的间隔物。 由于倾斜注射造成的损伤，翅片上的间隔物材料可以被蚀刻，具有比栅极叠层上的间隔物材料更高的选择性。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2005311367A

公开(公告)日：2005-11-04

申请号：JP2005119125

申请日：2005-04-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  DORIS BRUCE B ,  GUARINI KATHRYN W ,  LEONG MEIKEI ,  NARASIMHA SHREESH ,  REZNICEK ALEXANDER ,  KERN LIM ,  SADANA DEVENDRA K ,  SHI LEATHEN ,  SLEIGHT JEFFREY W ,  YANG MIN

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor device formed on a substrate having different crystal orientation.
SOLUTION: A method of forming a hybrid substrate containing strained Si and a strained Si containing hybrid substrate formed by this method are provided. In the present invention, a strained Si layer is formed on a semiconductor material, a second semiconductor layer, or both of them. According to the present invention, the strained Si layer has the same crystal orientation as either of a regrown semiconductor layer or the second semiconductor layer. This method provides the hybrid substrate wherein at least one of device layers contains the strained Si.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供形成在具有不同晶体取向的基板上的集成半导体器件。 解决方案：提供一种形成含有应变Si的混合基板和通过该方法形成的包含应变的含Si混合基板的方法。 在本发明中，在半导体材料，第二半导体层或它们两者上形成应变Si层。 根据本发明，应变Si层具有与重新生长的半导体层或第二半导体层中的任一个相同的晶体取向。 该方法提供混合基板，其中装置层中的至少一个包含应变Si。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004214627A

公开(公告)日：2004-07-29

申请号：JP2003396333

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  DOKUMACI OMER H ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/28114 ,  H01L21/26586 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665

Abstract: PROBLEM TO BE SOLVED: To provide an FET device in which the gate activity, line resistance and S/D extension resistance are improved. SOLUTION: A method for manufacturing a semiconductor transistor device is provided with following steps: a semiconductor substrate is formed; the semiconductor substrate has a gate dielectric layer on its surface; lower gate electrode structure is formed on the surface of the gate dielectric layer and the lower gate electrode structure has a low gate upper surface; a planarized layer is formed on the gate dielectric layer so that the upper part of the lower gate electrode structure is left in an exposed state; upper gate structure is formed on the lower gate electrode structure to form a T-type gate electrode; the lower surface of the upper gate structure and the vertical sidewall of the gate electrode are exposed; the planarized layer is removed; a source/drain extension is formed in the substrate protected from a short channel effect; a sidewall spacer is formed adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewall of the T-type gate electrode. A source/drain region is formed in the substrate. A silicide layer is formed on the upper part of the T-type gate electrode and the upper part of the source/drain region. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：WO2007087127A3

公开(公告)日：2007-11-22

申请号：PCT/US2007000161

申请日：2007-01-03

Applicant: IBM ,  CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WANG YUN Y ,  KWONG HON WONG KEITH

Inventor： CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WANG YUN Y ,  KWONG HON WONG KEITH

IPC: H01L21/336

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal- oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.

Abstract translation: 提供半导体结构，例如场效应晶体管（FET）和/或金属氧化物半导体电容器（MOSCAP），其中通过将金属杂质引入到含金属的物质中来改变导电电极堆叠的功函数 材料层与导电电极一起存在于电极堆叠中。 金属杂质的选择取决于电极是否具有n型功函数或p型功函数。 本发明还提供一种制造这种半导体结构的方法。 金属杂质的引入可以通过共沉积含有金属的材料和改变金属杂质的功函数的层来形成，形成其中金属杂质层存在于含金属材料的层之间的叠层，或通过形成 包括在含金属材料上方和/或下面的金属杂质的材料层，然后加热该结构，使得金属杂质被引入到含金属的材料中。