公开(公告)号：KR1020040033601A

公开(公告)日：2004-04-28

申请号：KR1020020062753

申请日：2002-10-15

Applicant: 한국전자통신연구원

Inventor： 신용우 ,  최상국 ,  김대용 ,  강동열

IPC: G02B7/02

Abstract: PURPOSE: A method for fabricating a micro column is provided to form correctly a plurality of opening portions regardless of an alignment error between micro lens forming elements by adhering micro lens formation elements and forming the opening portions at each center of the micro lens formation elements. CONSTITUTION: A plurality of insulating spacers(215,225,235) are located among micro lens formation elements(210,220,230). A plurality of opening portions(211,221,231) are formed at each center of the insulating spacers(215,225,235), respectively. The insulating spacers(215,225,235) and the micro lens formation elements(210,220,230) are alternately adhered to each other. The opening portions(211,221,231) of the insulating spacers(215,225,235) are formed by using a focused ion beam(240).

Abstract translation: 目的：通过粘附微透镜形成元件并在微透镜形成元件的每个中心处形成开口部分，提供用于制造微柱的方法，以正确地形成多个开口部分，而不管微透镜形成元件之间的对准误差如何。 构成：多个绝缘间隔物（215,225,235）位于微透镜形成元件（210,220,230）之间。 分别在绝缘间隔物（215,225,235）的每个中心处形成多个开口部分（211,221,231）。 绝缘间隔物（215,225,235）和微透镜形成元件（210,220,230）彼此交替地粘附。 通过使用聚焦离子束（240）形成绝缘间隔物（215,225,235）的开口部分（211,221,231）。

公开(公告)号：KR1020030092213A

公开(公告)日：2003-12-06

申请号：KR1020020029796

申请日：2002-05-29

Applicant: 한국전자통신연구원

Inventor： 임을균 ,  곽창수 ,  정해빈 ,  김대용 ,  안치득

IPC: G03B35/00

CPC classification number: G03B35/10 ,  G02B27/26 ,  H04N13/194 ,  H04N13/239 ,  H04N13/246

Abstract: PURPOSE: A single lens stereo camera and stereo image system using the same are provided to allow a user to view a stereo image by displaying an image taken through the monocular stereo camera. CONSTITUTION: A monocular single lens stereo camera includes an anamorphic optical system(31) for converting an aspect ratio of a screen and a biprism(32) for separating a left image from a right image. The single lens stereo camera also has a lens(12) and a camera body(11). The camera body(11) transmits a photographed image signal to a computer(35). The computer(35) is connected to the camera body(11) through a communication cable(33) so as to process the photographed image signal. An image splitting program, an image processing program, and an image distortion compensating program are stored in the computer(35).

Abstract translation: 目的：提供使用其的单透镜立体相机和立体声图像系统，以允许用户通过显示通过单眼立体相机拍摄的图像来观看立体图像。 构成：单眼单透镜立体相机包括用于转换屏幕的宽高比和用于将左图像与右图像分离的双棱镜（32）的变形光学系统（31）。 单透镜立体相机还具有透镜（12）和照相机主体（11）。 相机主体（11）将拍摄的图像信号发送到计算机（35）。 计算机（35）通过通信电缆（33）连接到照相机主体（11），以处理拍摄的图像信号。 图像分割程序，图像处理程序和图像失真补偿程序被存储在计算机（35）中。

公开(公告)号：KR100392370B1

公开(公告)日：2003-08-19

申请号：KR1020000083168

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 김진규 ,  엄낙웅 ,  김대용

IPC: G06F11/00

Abstract: PURPOSE: An inverse calculation system is provided to calculate an inverse of an arbitrary element by every one frequency of an externally transmitted clock in a Galois field used in an error correction system or an encryption system. CONSTITUTION: The system comprises an 8th power operator(201), multipliers(202, 209, 210, 213) registers(203, 204, 211, 212), a 128th power operator(205), a 2nd power operator(206), a 4th power operator(207) and an 8th power operator(208). The 8th power operator(201) raises an externally input primitive element to the power 8. The multiplier(202) multiplies the externally input primitive element by the number raised to the power 8. The register(203) stores the externally input primitive element. The register(204) stores a result operated by the multiplier(202). The 128th power operator(205) raises the number, stored at the register(203), to the power 128. The power operators(206, 207, 208) raise the number, stored at the register(204), to the power 2, 4, 8, respectively. The multiplier(209) multiplies the number, output by the power operator(205), by the number, output by the power operator(206). The multiplier(210) multiplies the number, output by the power operator(207), by the number, output by the power operator(208). The registers(211, 212) store the numbers output by the multipliers(209, 210), respectively. The multiplier(213) multiplies the number of the register(211) by the number of the register(212).

Abstract translation: 目的：提供反向计算系统，用于在错误校正系统或加密系统中使用的伽罗瓦域中，通过外部发送时钟的每一个频率来计算任意元素的倒数。 该系统包括第8个功率算子（201），乘法器（202,209,210,213），寄存器（203,204,211,212），第128个功率算子（205），第2个功率算子（206） 第四电力运营商（207）和第八电力运营商（208）。 第八功率算子（201）将外部输入的原始元素提升为功率8.乘法器（202）将外部输入的原始元素与提高到功率8的数相乘。寄存器（203）存储外部输入的原始元素。 寄存器（204）存储由乘法器（202）操作的结果。 第128个电力运营商（205）将存储在寄存器（203）处的号码提高到电力128.电力运营商（206,207,208）将存储在寄存器（204）处的号码提高到电力2 ，4，8。 乘法器（209）将功率运算器（205）输出的数量乘以功率运算器（206）输出的数量。 乘法器（210）将功率运算器（207）输出的数量乘以功率运算器（208）输出的数量。 寄存器（211,212）分别存储由乘法器（209,210）输出的数字。 乘法器（213）将寄存器（211）的号码乘以寄存器（212）的号码。

公开(公告)号：KR100328126B1

公开(公告)日：2002-08-14

申请号：KR1019980051086

申请日：1998-11-26

Applicant: 한국전자통신연구원

Inventor： 남기수 ,  노태문 ,  구진근 ,  김대용

IPC: H01L29/786

Abstract: 액티브 매트릭스 액정 디스플레이( AMLCD : Active Matrix Liquid Crystal Display) 및 EL 디스플레이에서 패널의 픽셀 어레이 스윗치와 주변 구동 집적회로에 이용되는 트렌치 게이트를 구비한 다결정 실리콘 박막 트랜지스터의 제조방법이 개시된다. 본 발명은 실리콘 또는 석영, 유리기판 위에 수평으로 구성되어 있는 게이트 구조를 트렌치 기술을 이용하여 수직으로 게이트를 구성한 트렌치 게이트 구조를 갖는 다결정 실리콘 박막 트랜지스터를 제조함으로써, 소자가 차지하는 면적을 줄일 뿐만 아니라 구동 전류의 감소 없이 고 전압에서 동작 할 수 있다

公开(公告)号：KR100347517B1

公开(公告)日：2002-08-07

申请号：KR1019990054156

申请日：1999-12-01

Applicant: 한국전자통신연구원

Inventor： 김도훈 ,  정해빈 ,  김대용

IPC: H01L21/027

Abstract: 본발명은노광장비의조명광학계에있어서노광장비의초점심도와해상도를증가시키기위하여복굴절광학부품을사용한리소그래피장비의변형조명장치를제공하는데그 목적이있다. 본발명에따르면, 광원으로부터입사되는빛을일정한모양으로정형하기위한광속확대기와파리눈렌즈인터그레이터(Fly's Eye Integrator), 상기광속확대기로부터전달되는광을효율적으로상기파리눈렌즈인터그레이터에전달하기위한줌 렌즈및 변형조명(Modified Illumination)을위하여상기파리눈렌즈인터그레이터에삽입되어있는변형조명판을포함하여이루어진리소그래피(Lithography) 장비의변형조명장치에있어서, 상기광속확대기로부터입사된빛을변형조명으로생성하여상기파리눈렌즈인터그레이터에전달하고, 조명에너지의손실을감소시키기위한다수의복굴절광학부로이루어져있는복굴절광학유니트를포함하여이루어진것을특징으로하는리소그래피장비의변형조명장치가제공된다.

公开(公告)号：KR1020020054213A

公开(公告)日：2002-07-06

申请号：KR1020000083237

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 김명환 ,  엄낙웅 ,  김대용

IPC: G11C29/00

Abstract: PURPOSE: A test apparatus for testing automatically an internal memory of a semiconductor device is provided to perform automatically a test operation for a memory which is installed in a semiconductor device. CONSTITUTION: A scan circuit(103) is connected with an internal circuit(101), a pattern generator(102), and a data input buffer(104) in order to select pattern data in a test process or internal data in a normal process. A data input buffer(104) is connected with the scan circuit(103) and a memory cell(105) in order to buffer the data from the scan circuit(103). The memory cell(105) is connected with the data input buffer(104) and a data output buffer(108) in order to receive the data from the data input buffer(104) and transmit the data to the data output buffer(108). A comparing pattern generator(106) is connected with the pattern generator(102), a comparing result control circuit(109), the memory cell(105), and a comparator(107). The data output buffer(108) is connected with the memory cell(105) and the comparator(107). The comparator(107) is connected with the comparing pattern generator(106) and the data output buffer(108). The comparing result control circuit(109) controls the pattern generator(102) and the comparing pattern generator(106). A state display portion(110) is connected with the comparator(107).

Abstract translation: 目的：提供一种用于自动测试半导体器件的内部存储器的测试装置，以自动执行安装在半导体器件中的存储器的测试操作。 构成：扫描电路（103）与内部电路（101），模式发生器（102）和数据输入缓冲器（104）连接，以便在测试过程中选择模式数据或在正常处理中选择内部数据 。 数据输入缓冲器（104）与扫描电路（103）和存储单元（105）连接，以缓冲来自扫描电路（103）的数据。 存储单元（105）与数据输入缓冲器（104）和数据输出缓冲器（108）连接，以从数据输入缓冲器（104）接收数据，并将数据发送到数据输出缓冲器（108） 。 比较模式发生器（106）与模式发生器（102），比较结果控制电路（109），存储单元（105）和比较器（107）相连。 数据输出缓冲器（108）与存储单元（105）和比较器（107）连接。 比较器（107）与比较模式发生器（106）和数据输出缓冲器（108）连接。 比较结果控制电路（109）控制图案生成器（102）和比较图案生成器（106）。 状态显示部分（110）与比较器（107）连接。

公开(公告)号：KR1020020051302A

公开(公告)日：2002-06-28

申请号：KR1020000080909

申请日：2000-12-22

Applicant: 한국전자통신연구원

Inventor： 박기혁 ,  엄낙웅 ,  김대용

IPC: G06F7/52

Abstract: PURPOSE: A calculation circuit for adding/subtracting an output of a multiplier to/from at least one input signal is provided to realize a high speed operation without increasing a size of hardware in embodying a calculation circuit. CONSTITUTION: A partial product creating unit(401) is provided for creating a plurality of partial products by a multiplier and a multiplicand. A partial product adding unit(402) adds the partial products to more than one input signal simultaneously for outputting a partial sum and a carry. A carry-propagate adder(403) is provided for outputting a multiplication value by finally adding the partial sum of the partial product adding unit(402) to the carry. The input signal is a 2's complement converted signal. The partial product adding unit(402) is embodied by a multiple input parallel adder.

Abstract translation: 目的：提供一种用于向/从至少一个输入信号增加/减少乘法器的输出的计算电路，以在不增加体现计算电路中的硬件的大小的情况下实现高速操作。 构成：提供部分产品创建单元（401），用于通过乘法器和被乘数来创建多个部分乘积。 部分积添加单元（402）将部分乘积同时添加到多个输入信号以输出部分和和进位。 提供进位传播加法器（403），用于通过最终将部分乘积加法单元（402）的部分和加到进位来输出乘法值。 输入信号是2的补码转换信号。 部分积添加单元（402）由多输入并行加法器实现。

公开(公告)号：KR1020010064243A

公开(公告)日：2001-07-09

申请号：KR1019990062393

申请日：1999-12-27

Applicant: 한국전자통신연구원

Inventor： 김명환 ,  곽명신 ,  김대용

IPC: G11C29/00

Abstract: PURPOSE: A latch and memory testing circuit is provided to detects latch and memory malfunctions and to detect various malfunction by using effective testing patterns. CONSTITUTION: The latch and memory testing circuit includes a test pattern generator(105), a data temporary input member(101), a data temporary output member(104), the first data comparator(106), the second data comparator(108) and a clock blocker. The test pattern generator(105) generates test patterns. The data temporary input member(101) buffers the data input from the test pattern generator(105). The data temporary output member(104) buffers the data output from the memory cell. The first data comparator(106) compares the input data with the output data and determines the malfunction of the memory cell. The second data comparator(108) compares the input data with the output data and determines the malfunction of the latch. The clock blocker terminates clock generating when malfunction occurs in the memory cell and the latch.

Abstract translation: 目的：提供锁存和存储器测试电路以检测锁存和存储器故障，并通过使用有效的测试模式来检测各种故障。 构成：锁存和存储器测试电路包括测试码型发生器（105），数据临时输入元件（101），数据临时输出元件（104），第一数据比较器（106），第二数据比较器（108） 和时钟阻滞器。 测试模式发生器（105）产生测试模式。 数据临时输入构件（101）缓冲从测试图案发生器（105）输入的数据。 数据临时输出构件（104）缓冲从存储单元输出的数据。 第一数据比较器（106）将输入数据与输出数据进行比较，并确定存储单元的故障。 第二数据比较器（108）将输入数据与输出数据进行比较，并确定锁存器的故障。 当存储器单元和锁存器发生故障时，时钟阻断器终止时钟产生。

公开(公告)号：KR1020010048980A

公开(公告)日：2001-06-15

申请号：KR1019990053887

申请日：1999-11-30

Applicant: 한국전자통신연구원

Inventor： 최상수 ,  이진희 ,  김도훈 ,  이각현 ,  정해빈 ,  김대용

IPC: H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/28593 ,  H01L29/42316

Abstract: PURPOSE: A method for manufacturing a gamma gate of a high electron mobility transistor(HEMT) is provided to remarkably reduce device noise, by sufficiently increasing the head of the gamma gate in area. CONSTITUTION: The first resist is applied on a GaAs substrate. After an exposure and development process, the first resist is hardened to form the first resist pattern. The second resist is applied on the GaAs substrate and the first resist pattern. After an exposure and development process, the second resist is hardened to form the second resist pattern. A portion of the GaAs substrate not covered by the first and second resist patterns is defined as a region(103) where the footprint of the gamma gate is formed. A portion of the GaAs substrate not covered by the second resist pattern but covered by the first resist pattern is defined as a region(102) where the head of the gamma gate is formed.

Abstract translation: 目的：提供一种制造高电子迁移率晶体管（HEMT）的伽马栅的方法，通过充分增加伽马门的头部区域，显着降低器件噪声。 构成：将第一抗蚀剂施加在GaAs衬底上。 在曝光和显影处理之后，第一抗蚀剂被硬化以形成第一抗蚀剂图案。 将第二抗蚀剂施加在GaAs衬底和第一抗蚀剂图案上。 在曝光和显影处理之后，第二抗蚀剂被硬化以形成第二抗蚀剂图案。 未被第一和第二抗蚀剂图案覆盖的GaAs衬底的一部分被定义为形成伽马栅的覆盖区的区域（103）。 GaAs衬底的未被第二抗蚀剂图案覆盖但被第一抗蚀剂图案覆盖的部分被定义为形成伽马栅的头部的区域（102）。

公开(公告)号：KR1020010027910A

公开(公告)日：2001-04-06

申请号：KR1019990039890

申请日：1999-09-16

Applicant: 한국전자통신연구원

Inventor： 김충환 ,  김천수 ,  유현규 ,  박민 ,  김대용

IPC: H03D7/00

Abstract: PURPOSE: A mixer of Gibert cell frequency by using a unipolar switch is provided to reduce loss of gain of converting by supplying the condition of bias optimized by the operation of a unipolar switch. CONSTITUTION: A mixer of Gibert cell frequency by using a unipolar switch includes six FETs(Field Effect Transistors). The radio frequency signal is permitted to the gate of a FET(F311) and the electric current lD1 flows in the drain. The reverse radio frequency signal is permitted to the gate of a FET(F312) and the electric current lD2 flows in the drain. The partial oscillator signal is permitted to the gate of the FET(F313) and the drain of the FET(F313) is connected to the source of the FETs(F311, F312) in common. The radio frequency signal(RF) is permitted to the gate of the FET(F314) and the electric current lD3 flows in the drain connected with the drain of the FET(F311). The reverse radio frequency signal(/RF) is permitted to the gate of the FET(F315) and the electric current lD4 flows in the drain connected with the drain of the FET(F312). The the reverse partial oscillator signal(/LO) is permitted to the gate of the FET(F316) and the drain is connected to the source of the FETs(F314, F315) in common.

Abstract translation: 目的：提供通过使用单极开关的Gibert电池频率的混频器，通过提供通过单极开关的操作优化的偏置条件来减少转换增益的损失。 构成：使用单极开关的Gibert电池频率的混频器包括六个FET（场效应晶体管）。 射频信号被允许到FET的栅极（F311），电流ID1流入漏极。 反向射频信号被允许到FET的栅极（F312），并且电流ID2流入漏极。 部分振荡器信号被允许到FET的栅极（F313），并且FET（F313）的漏极共同连接到FET的源极（F311，F312）。 允许射频信号（RF）到FET（F314）的栅极，并且电流ID3流过与FET（F311）的漏极连接的漏极。 反向射频信号（/ RF）被允许到FET的栅极（F315），并且电流ID4流过与FET的漏极连接的漏极（F312）。 反向部分振荡器信号（/ LO）被允许到FET（F316）的栅极，漏极与FET（F314，F315）的源极共同连接。