公开(公告)号：JPH0898512A

公开(公告)日：1996-04-12

申请号：JP22351895

申请日：1995-08-31

Applicant: ST MICROELECTRONICS SRL

Inventor： NICOLLINI GERMANO ,  CONFALONIERI PIERANGELO

IPC: H01L27/04 ,  H01L21/822 ,  H02M3/07

Abstract: PROBLEM TO BE SOLVED: To stably maintain an output voltage and practically independent of a power supply voltage, a temperature, a process and within a certain limit, a load absorption current. SOLUTION: In an output voltage stabilization circuit which is composed of an input terminal IN, an output terminal OUT, a charge transmission capacitor C1 which takes out charges from the input terminal IN and transmits the charge to the output terminal OUT and an integrator, whose input is connected to the output terminal of a voltage multiplier and which generates a continuous voltage, corresponding to the difference between a reference voltage Vrif and the output voltage Vout of the voltage multiplier, the continuous voltage is supplied to one of the terminals of a charge transmission capacitor C1.

公开(公告)号：JPH0878630A

公开(公告)日：1996-03-22

申请号：JP13179495

申请日：1995-05-30

Applicant: ST MICROELECTRONICS SRL

Inventor： RAVANELLI ENRICO ,  ZULLINO LUCIA

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06

Abstract: PURPOSE: To provide a small area protective device, having high efficiency in energy and response speed, which protects a semiconductor MOS integrated circuit from electrostatic discharges on an input/output terminal. CONSTITUTION: A first region 15 and a third region 20 of a second conductivity- type N are separately protruded into a first conductivity-type P surface zones 12 and 13 from the main surface of a wafer, a second region 18 is protruded into a first region 15, and a SCR, having terminals 22 and 24 of a conductive material, which is brought into ohmic contact with the second region 18 and the third region 20, is provided. In the device, having a reverse breakdown potential, in which the joint part of the first region 15 and the surface zones 12 and 13 prescribe the starting potential of the SCR, a conductive layer 17 is insulated from the first region 15 and is extended crossing the edge part of the conductive layer 17. The reverse breakdown potential of the joint part can be decreased to the prescribed value, and polarity can be given to the conductive layer 17, so that the distribution of the electric field on the junction part can be changed.

公开(公告)号：JPH0864811A

公开(公告)日：1996-03-08

申请号：JP19326495

申请日：1995-07-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/78 ,  H01L29/739

Abstract: PROBLEM TO BE SOLVED: To prevent trigger-ons of a parasitic thyristor and to reduce static losses by allowing the sum of the common base current gain of a first bipolar junction type transistor and the current gain of a second bipolar junction type transistor to be 1 or greater. SOLUTION: A source region 11, a channel region 7, and an n-type layer 3 constitute a power MOSFET. The source region 11, a main body region 2, and the n-type layer 3 form the first npn bipolar junction type transistor T1. Furthermore, a substrate 5, the n-type layer 3, and the main body region constitute the second pnp bipolar junction type transistor T2. The sum of base current gains αn and αp of the npn bipolar junction type transistor T1 and pnp bipolar junction type transistor T2 are set so as to be 1 or greater. When the power MOSFET is driven on, both transistors are biased in the forward direction, resulting in αn +αp

公开(公告)号：JPH0863953A

公开(公告)日：1996-03-08

申请号：JP4930295

申请日：1995-02-15

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA

IPC: G11C17/00 ,  G11C5/14 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

Abstract: PURPOSE: To obtain a load signal generating method and circuit for a non- volatile memory. CONSTITUTION: A circuit 1 is used to generate a variable length data load pulse L depending on the requirement and is provided with a source 5 for applying a short load signal SP and a delay element 19 for generating a long pulse STP when the short load signal appears. Static operation mode is given so that a load pulse is generated continuously through the static operation so long as the critical state (standby condition, low voltage) is continued. An expanded pulse is always generated when the static operation mode terminates, while a delay element 19 is disabled by a command EN when the expanded timing is not required.

公开(公告)号：JPH0855921A

公开(公告)日：1996-02-27

申请号：JP9322995

申请日：1995-03-28

Applicant: ST MICROELECTRONICS SRL

Inventor： DALLABORA MARCO ,  SALI MAURO LUIGI ,  TASSAN CASER FABIO ,  VILLA CORRADO

IPC: H01L21/8247 ,  G11C16/04 ,  G11C16/16 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide a NOR flash type memory array corresponding to the programming of small current without changing any auxiliary element such a decode, sense and load devices. CONSTITUTION: Concerning a flash EEPROM memory array 35, asymmetric structure is provided by memory cells 36 having source areas composed of row/column style and connected to respective bit lines BL, source regions connected to common source lines BLS and control gate regions connected to respective work lines WL and in that asymmetric structure, either the source region or the drain region provides a high resistant section so that the cells in various areas can be programmed and erased. The memory array 35 includes a bias transistor 41 for preventing spurious writing by keeping the drain region and source region of cell connected to the bit line, to which any address is not designated, at the same potential when programming.

公开(公告)号：JPH0855436A

公开(公告)日：1996-02-27

申请号：JP32378294

申请日：1994-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： GADDUCCI PAOLO ,  MOLONEY DAVID ,  BETTI GIORGIO

IPC: G11B20/14 ,  G11B20/10 ,  G11B20/18 ,  H04B15/00

Abstract: PURPOSE: To provide a survival sequence register of a simple structure having high reliability, by receiving a stream of logical sum of serial input streams SWP and SWN from G1, causing a first shift register F7 -F14 to remove spurious components, and causing a control circuit to generate an erase signal. CONSTITUTION: A survival sequence register is supplied with inputs of coded digital signals SWP, SWN corresponding to positive/negative certification peaks from a pickup and a clock signal CLK, and includes a variable threshold qualification circuit. The survival sequence register receives a logical sum output of SWP, SWN from an OR circuit G1 and removes spurious components by a shift register made of flip-flops F7 -F14 . A control circuit generates an erase signal. A second pointer shift register shifts through F7 -F14 and points out logic '1' of a sequence preceding logic '1' corresponding to a detection peak of the same code corresponding to the preceding logic '1'. With this structure, an SSR for variable threshold certification for channel recording having a simple structure and high reliability may be provided.

公开(公告)号：JPH0851190A

公开(公告)日：1996-02-20

申请号：JP18343595

申请日：1995-06-26

Applicant: ST MICROELECTRONICS SRL

Inventor： MARCHIO FABIO ,  PENNISI ALESSIO

IPC: H01L27/04 ,  G01R31/28 ,  G05F1/56 ,  H01L21/822 ,  H01L23/58

Abstract: PURPOSE: To provide a voltage regulator which can detect ruptures of bonding wires for connecting a pad and a lead at the final test of a final product, i.e., an integrated circuit. CONSTITUTION: A voltage regulator includes a connection path having resistors (Ra and Rb) lower than resistors (R1 and R2) constituting a sense voltage divider between pads at least by a factor of two figures.

公开(公告)号：JPH0846488A

公开(公告)日：1996-02-16

申请号：JP9729995

申请日：1995-04-21

Applicant: ST MICROELECTRONICS SRL

Inventor： NICOLLINI GERMANO ,  NAGARI ANGELO

IPC: G11C27/02 ,  H03F3/00 ,  H03H19/00 ,  H03K5/24

Abstract: PURPOSE: To provide a switching capacitor circuit lowering harmonic wave distortion without considerably increasing the complexity of circuit and the area required for integration as an integrated circuit. CONSTITUTION: This circuit has one operational amplifier (OA) 2 at least having 1st and 2nd input terminals at least and a 1st output terminal at least and connecting the 1st input terminal to a 1st reference potential and at this switching capacitor circuit provided with one negative feedback network at least provided with a capacitor C2 at the OA2 while having the 2nd input terminal through a switch SW1, the 1st terminal alternately connected to the 1st reference potential and the 2nd terminal connected through a switch SW2 alternately to a circuit node A connected to the 1st input and output terminals of OA2, a capacitor CX is provided at least while being connected between the circuit node A and a 2nd reference potential.

公开(公告)号：JPH0846487A

公开(公告)日：1996-02-16

申请号：JP16657095

申请日：1995-06-30

Applicant: ST MICROELECTRONICS SRL

Inventor： DALLE FESTE SANDRO ,  BIANCHESI MARCO ,  CREMONESI ALESSANDRO

IPC: H03H15/00 ,  H03H17/00 ,  H03H17/02 ,  H03H17/06

Abstract: PURPOSE: To satisfy timewise limitation conditions to filter components with a filter having serial architecture with a finite impulse response(FIR) while having a simple controller. CONSTITUTION: This oversampling digital filter is composed of a memory means M1 for coefficients, memory means M2 for sampling signals to be filtered, multiplier MU connected to the output terminals of memory means M1 and M2, accumulator AC connected to the output terminal of that multiplier MU, and simple controller CU for controlling elements based on a clock signal CLK received at the input terminal of that accumulator.

公开(公告)号：JPH0846069A

公开(公告)日：1996-02-16

申请号：JP7625895

申请日：1995-03-31

Applicant: ST MICROELECTRONICS SRL

Inventor： PALMIERI MICHELE ,  DEPETRO RICCARDO

IPC: H01L21/8249 ,  H01L21/225 ,  H01L21/265 ,  H01L21/329 ,  H01L21/331 ,  H01L21/337 ,  H01L21/822 ,  H01L27/06 ,  H01L29/73 ,  H01L29/866

Abstract: PURPOSE: To reduce the dependency on the process parameters of the concentration and/or depth of a buried region, by allowing a second impurity addition stage to have a first sub-step for performing implantation with a low energy and a second sub-step for performing implantation by a low amount of addition and a high energy. CONSTITUTION: When a semiconductor device with a buried junction is manufactured, the impurity in a first format (arsenic) and a second formal (boron) is successively introduced into a silicon chip by the first and second impurity addition stages. An introduced impurity is diffused by a high-temperature treatment, thus forming first and second regions 32 and 33. The amount of impurity to be added and an implantation energy are at a level so that the conduction format (N) of the first region 32 cannot be canceled or inverted, and a concentration at the second region 33 essentially depends on only a second implantation.