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    FINE ELECTRIC MECHANICAL SWITCH
    22.
    发明专利
    FINE ELECTRIC MECHANICAL SWITCH 审中-公开

    公开(公告)号：JP2003249137A

    公开(公告)日：2003-09-05

    申请号：JP2002330991

    申请日：2002-11-14

    Applicant: IBM

    Inventor： GREENBERG DAVID R ,  DELIGIANNI HARIKLIA ,  ROBERT A GROVES ,  CHRISTOPHER V JARNES ,  LUND JENNIFER L ,  CATHERINE L SAENGER ,  VOLANT RICHARD P

    IPC: B81B3/00 ,  H01H1/24 ,  H01H1/26 ,  H01H59/00

    Abstract: PROBLEM TO BE SOLVED: To provide a fine electric mechanical switch having a restoring force large enough to overcome static friction. SOLUTION: This fine electric mechanical switch comprises a conductive beam 10 capable of being warped, and a plurality of electrodes which are covered with elastically deformable conductive layers 11. At first, a restoring force is generated by a single spring constant k0 of the beam 10 by applying a control voltage between the beam 10 capable of being warped and a control electrode 12 which is flush with a switch electrode 13. Then, when the fine electric mechanical switch is approached to the closed state and the conductive layers 11 are compressed, restoring forces due to additional spring constants, k1,..., kn of the plurality of deformable conductive layers 11 are sequentially added to the restoring force due to the spring constant k0 of the beam 10. In another embodiment, deformable spring-like elements are used in place of the deformable layers. Furthermore in the other embodiment, compressible layers or the deformable spring-like elements are mounted on the warping beam which is opposed to the switch electrode. COPYRIGHT: (C)2003,JPO

    METHOD OF FORMING A MULTI-CHIP STACKED STRUCTURE INCLUDING A THIN INTERPOSER CHIP HAVING A FACE-TO-BACK BONDING WITH ANOTHER CHIP
    26.
    发明申请
    METHOD OF FORMING A MULTI-CHIP STACKED STRUCTURE INCLUDING A THIN INTERPOSER CHIP HAVING A FACE-TO-BACK BONDING WITH ANOTHER CHIP 审中-公开
    形成多芯片堆叠结构的方法，其中包括具有另一个芯片的面对背结合的薄间隙芯片

    公开(公告)号：WO2011119308A3

    公开(公告)日：2011-12-29

    申请号：PCT/US2011026957

    申请日：2011-03-03

    Applicant: IBM ,  FAROOQ MUKTA G ,  PETRARCA KEVIN S ,  VOLANT RICHARD P

    Inventor： FAROOQ MUKTA G ,  PETRARCA KEVIN S ,  VOLANT RICHARD P

    IPC: H01L23/48 ,  H01L23/12

    CPC classification number: H01L21/6835 ,  H01L23/3128 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/00

    Abstract: A temporary substrate (901) having an array of first solder pads (192) is bonded to the front side of a first substrate (101) by reflowing an array of first solder balls (250). The first substrate (101) is thinned by removing the back side, and an array of second solder pads (142) is formed on the back side surface of the first substrate (101). The assembly of the first substrate (101) and the temporary substrate (901) is diced to form a plurality of stacks, each including an assembly of a first semiconductor chip (100) and a handle portion (900). A second semiconductor chip (200) is bonded to an assembly through an array of the second solder balls (150). The handle portion (900) is removed from each assembly by reflowing the array of the first solder balls (250), while the array of the second solder balls (150) does not refiow. The assembly is subsequently mounted on a packaging substrate (300) employing the array of the first solder balls (250).

    Abstract translation: 具有第一焊盘（192）的阵列的临时衬底（901）通过回流第一焊球（250）的阵列而接合到第一衬底（101）的前侧。 通过去除背面而使第一衬底（101）变薄，并且在第一衬底（101）的背侧表面上形成有第二焊盘（142）的阵列。 切割第一基板（101）和临时基板（901）的组装以形成多个堆叠，每个堆叠包括第一半导体芯片（100）和手柄部分（900）的组件。 第二半导体芯片（200）通过第二焊球（150）的阵列结合到组件。 通过回流第一焊球（250）的阵列，而第二焊球（150）的阵列不反射，从每个组件移除手柄部分（900）。 随后，使用第一焊球（250）的阵列将组件安装在包装衬底（300）上。

    OPTIMIZED ANNULAR COPPER TSV
    27.
    发明申请
    OPTIMIZED ANNULAR COPPER TSV 审中-公开
    优化的环形铜片TSV

    公开(公告)号：WO2012177585A3

    公开(公告)日：2013-04-25

    申请号：PCT/US2012043052

    申请日：2012-06-19

    Applicant: IBM ,  ANDRY PAUL S ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K ,  VOLANT RICHARD P

    Inventor： ANDRY PAUL S ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K ,  VOLANT RICHARD P

    IPC: H01L21/28 ,  H01L21/768

    CPC classification number: H01L21/76846 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

    Abstract translation: 本公开提供了热机械可靠的铜TSV和在BEOL处理期间形成这种TSV的技术。 TSV构成延伸穿过半导体衬底的环形沟槽。 衬底限定沟槽的内侧壁和外侧壁，该侧壁分隔5至10微米的距离。 包括铜或铜合金的导电路径从所述第一介电层的上表面通过所述衬底在所述沟槽内延伸。 基板厚度可以为60微米或更小。 具有导电连接到导电路径的互连金属化的电介质层直接形成在所述环形沟槽上。

    Optimized annular copper TSV
    29.
    发明专利
    Optimized annular copper TSV 未知

    公开(公告)号：GB2505576B

    公开(公告)日：2016-03-23

    申请号：GB201318982

    申请日：2012-06-19

    Applicant: IBM

    Inventor： ANDRY PAUL S ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K ,  VOLANT RICHARD P

    IPC: H01L23/48 ,  H01L21/28 ,  H01L21/768

    Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

    30.
    发明专利
    未知

    公开(公告)号：DE60224836D1

    公开(公告)日：2008-03-13

    申请号：DE60224836

    申请日：2002-11-07

    Applicant: IBM

    Inventor： VOLANT RICHARD P ,  BISSON JOHN C ,  COTE DONNA R ,  DALTON TIMOTHY J ,  GROVES ROBERT A ,  PETRARCA KEVIN S ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

    IPC: B81C1/00 ,  B81B3/00 ,  H01H49/00 ,  H01H59/00

    Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

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