公开(公告)号：WO0195391A8

公开(公告)日：2002-03-28

申请号：PCT/US0117927

申请日：2001-06-01

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NESBIT LARRY ,  MCSTAY IRENE LENNOX ,  RADENS CARL ,  TEWS HELMUT HORST ,  DIVAKARUNI RAMA ,  MANDELMAN JACK

IPC: H01L21/8242

CPC classification number: H01L27/10861 ,  H01L27/10867

Abstract: A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner (81) is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer (79). A layer of amorphous silicon (83) is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist (83) is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar (89) along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.

Abstract translation: 一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。 首先在硅衬底中形成DRAM沟槽。 然后，氮化物衬垫（81）沉积在硅沟槽壁上。 氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层（79）上。 然后在氮化物衬垫上沉积一层非晶硅（83）。 在非晶硅的氧化表面上沉积氮化硅层。 在沟槽的下部形成抗蚀剂（83），去除非晶硅顶部的露出的氮化硅层，使非晶硅层的上部露出。 然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环（89）。 非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。 氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。 在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。

公开(公告)号：CZ20011964A3

公开(公告)日：2001-11-14

申请号：CZ20011964

申请日：1999-11-26

Applicant: IBM

Inventor： AGAHI FARID ,  HSU LOUIS ,  MANDELMAN JACK

IPC: H01L21/8242 ,  H01L27/108

Abstract: A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes. A signal transfer device has: (i) an annular signal transfer region with an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end; (ii) a first diffusion region coupling the first end of the signal transfer region to the. second electrode of the signal storage node; (iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor; (iv) a gate insulator coating the inner surface of the signal transfer region; and (v) a gate conductor coating the gate insulator and coupled to the word line. A conductive connecting member couples the signal transfer region to a reference voltage to reduce floating body effects.

公开(公告)号：DE602006018643D1

公开(公告)日：2011-01-13

申请号：DE602006018643

申请日：2006-10-27

Applicant: IBM

Inventor： HSU LOUIS LU-CHEN ,  MANDELMAN JACK ,  TONTI WILLIAM

IPC: H01L23/525

公开(公告)号：AT441938T

公开(公告)日：2009-09-15

申请号：AT06830385

申请日：2006-12-05

Applicant: IBM

Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  HSU LOUIS ,  YANG HAINING

IPC: H01L21/336 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/45 ,  H01L29/78

Abstract: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.

公开(公告)号：AT377841T

公开(公告)日：2007-11-15

申请号：AT02791319

申请日：2002-11-25

Applicant: IBM

Inventor： DORIS BRUCE ,  CHIDAMBARRAO DURESETI ,  IEONG MEIKEI ,  MANDELMAN JACK

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

公开(公告)号：AU2002343408A1

公开(公告)日：2003-04-01

申请号：AU2002343408

申请日：2002-09-17

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK

IPC: H01L29/41 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119 ,  H01L31/113

Abstract: A wrapped-gate transistor includes a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer is formed on the substrate. A gate electrode is formed on the gate dielectric layer to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric therebetween. The substrate is a silicon island formed on an insulation layer of an SOI (silicon-on-insulator) substrate or on a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the "body-to-source" voltage.

公开(公告)号：DE60129605D1

公开(公告)日：2007-09-06

申请号：DE60129605

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK ,  RUPP THOMAS

IPC: H01L21/00 ,  H01L27/10 ,  H01L21/8242

Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports.

公开(公告)号：AU2002351206A1

公开(公告)日：2004-06-23

申请号：AU2002351206

申请日：2002-12-03

Applicant: IBM

Inventor： VOLDMAN STEVEN H ,  MANDELMAN JACK

IPC: H01L21/336 ,  H01L23/62 ,  H01L27/02 ,  H01L27/12 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01

公开(公告)号：PL348501A1

公开(公告)日：2002-05-20

申请号：PL34850199

申请日：1999-11-26

Applicant: IBM

Inventor： AGAHI FARID ,  HSU LOUIS ,  MANDELMAN JACK

IPC: H01L21/8242 ,  H01L27/108

Abstract: A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes. A signal transfer device has: (i) an annular signal transfer region with an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end; (ii) a first diffusion region coupling the first end of the signal transfer region to the. second electrode of the signal storage node; (iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor; (iv) a gate insulator coating the inner surface of the signal transfer region; and (v) a gate conductor coating the gate insulator and coupled to the word line. A conductive connecting member couples the signal transfer region to a reference voltage to reduce floating body effects.

公开(公告)号：AT551727T

公开(公告)日：2012-04-15

申请号：AT04702490

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER ,  DORIS BRUCE ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

Abstract: A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.