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    22.
    发明专利
    未知

    公开(公告)号：DE59707158D1

    公开(公告)日：2002-06-06

    申请号：DE59707158

    申请日：1997-01-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TIHANYI JENOE ,  STRACK HELMUT ,  GEIGER HEINRICH

    IPC: H01L21/205 ,  H01L21/225 ,  H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

    Abstract: The device has a drain zone (1,2) of a first conductivity type and a relatively insulated polycrystalline silicon gate electrode (6), with at least one zone of opposite type incorporated in the drain zone within which a source zone of the first conductivity type is formed. The drain zone incorporates a doped region (15) of the first conductivity type, incorporating a number of zones (16) of the opposite type, with the overall doping of the zones corresponding to the doping of the doped region.The relative spacing of the doped zones is less than the width of the spatial charge zone between the region of first conductivity type and the doped zones.

    Power semiconductor device comprises vertical MOSFETs and insulated gate bipolar transistors as power semiconductor chip component, a stack from a vertical junction field effect transistor and MOSFET, bridge circuit, and cascade circuit
    28.
    发明专利
    Power semiconductor device comprises vertical MOSFETs and insulated gate bipolar transistors as power semiconductor chip component, a stack from a vertical junction field effect transistor and MOSFET, bridge circuit, and cascade circuit 未知

    公开(公告)号：DE102006021959A1

    公开(公告)日：2007-11-15

    申请号：DE102006021959

    申请日：2006-05-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： OTREMBA RALF ,  STRACK HELMUT

    IPC: H01L23/48 ,  H01L25/07 ,  H01L29/739 ,  H01L29/78

    Abstract: The power semiconductor device comprises vertical MOSFETs and insulated gate bipolar transistors as power semiconductor chip component (6), a stack from a vertical junction field effect transistor and the MOSFET, a bridge circuit, a cascade circuit made of stacked semiconductor chips, connecting elements (12) with circuit board segments (27) and through-contacts (25), and a bonding wire to a contact surface of a control electrode. The chip component has electrodes on its upper- and lower side with a large surface area. The power semiconductor device comprises vertical MOSFETs and insulated gate bipolar transistors as power semiconductor chip component (6), a stack from a vertical junction field effect transistor and the MOSFET, a bridge circuit, a cascade circuit made of stacked semiconductor chips, connecting elements (12) with circuit board segments (27) and through-contacts (25), and a bonding wire to a contact surface of a control electrode. The chip component has electrodes on its upper- and lower side with a large surface area. The electrodes extend almost along the entire chip component and are electrically connected over the connecting elements with external contacts (13). The chip component and the connecting elements are embedded in a plastic full package-housing, which has a compacted superimposed plastic layers (15, 16) with parallel and planar upper surfaces. On one of the upper surfaces, the connecting elements are arranged as a structured metal layer in a peripheral wiring layer and are electrically connected with the electrodes and the external contacts over the through-contacts that pass through one of the plastic layers. The metal layer is formed by means of a physical vapor deposition or by means of a galvanic or chemical deposition process, exhibits different layer thicknesses and comprises several connecting elements that are electrically isolated from one another. A further semiconductor chip and/or a passive component are arranged on the circuit board segments. The circuit board segment is intended as a chip-carrier. An upper region of the circuit board segment consists of a connection region for wire bonding. The lower sides of the power semiconductor device are plastic surfaces. An external flat-strip conductor protrudes out of the marginal sides of the plastic housings, which are embedded in a bottom plastic layer of the plastic housing. The second plastic layer encases the first layer of plastic and forms the outer contour of the plastic housing. The flat-strip conductor panel is made of a super SO or a TO 220 or TO 252 type of housing. The chip component is arranged in the lower plastic layer on a chip carrier with its lower-sided electrode and on a counter electrode with a large surface area exhibiting a smaller contact surface. The chip component is mounted on the chip carrier by means of diffusion solder, a soft solder or an electrically conductive adhesive. The circuit board segment with a lower thickness is covered by a second plastic layer. The thicker circuit board segment is held free of the second plastic layer. The connecting elements are embedded in a third plastic layer. Two b switches are arranged on the first plastic layer with the metal layer and two low-side switches are arranged on the circuit board segments and on the second plastic layer. A first semiconductor transistor is electrically connected with the flat-strip conductor over the first connecting element. The drain electrodes of the two high-side switches are mounted on the chip carrier and are electrically interconnected with one another. The two high-side switches are intended in a single semiconductor unit or are intended as separate power semiconductor chip components. An independent claim is included for a procedure for production of a power semiconductor device.

    30.
    发明专利
    未知

    公开(公告)号：AT334480T

    公开(公告)日：2006-08-15

    申请号：AT99929017

    申请日：1999-04-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DEBOY GERALD ,  STENGL JENS-PEER ,  STRACK HELMUT ,  WEBER HANS ,  GRAF HEIMO ,  RUEB MICHAEL ,  AHLERS DIRK

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

    Abstract: A semiconductor component has a semiconductor body comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode. The side of the zone of the second conductivity type facing the drain zone forms a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, comprises areas of the first and second conductivity type nested in one another. The second surface is positioned at a distance from the drain zone such that the areas of the first and second conductivity type nested in each other do not reach the drain zone.

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