公开(公告)号：KR1020030078299A

公开(公告)日：2003-10-08

申请号：KR1020020017252

申请日：2002-03-29

Applicant: 매그나칩 반도체 유한회사

Inventor： 이준석

IPC: H03M1/76

CPC classification number: H03M1/802 ,  H03M2201/6372

Abstract: PURPOSE: A linearity improved MDAC(Multiplying Digital to Analog Converter) is provided to secure linearity regardless of the error factors according to processes. CONSTITUTION: A linearity improved MDAC is provided with a capacitor array(30) having a plurality of unit capacitors(C1,C2,C3,C4) and an amplifying part(31) for outputting an analog signal by forming a feed-back loop with the unit capacitors. At this time, the unit capacitors selectively form the feed-back loop with the amplifying part according to an inputted digital code. Preferably, the linearity improved MDAC further includes a switching part for controlling the feed-back of the capacitor array according to the digital code.

Abstract translation: 目的：提供线性度改进的MDAC（乘法数字到模拟转换器），以确保线性度，而不考虑错误因素根据过程。 构成：具有线性改善MDAC的电容器阵列（30）具有多个单位电容器（C1，C2，C3，C4）和放大部件（31），用于通过形成反馈回路来输出模拟信号， 单位电容器。 此时，单位电容器根据输入的数字代码与放大部分选择性地形成反馈回路。 优选地，改善MDAC的线性度还包括根据数字代码来控制电容器阵列的反馈的开关部分。

公开(公告)号：KR1020030002464A

公开(公告)日：2003-01-09

申请号：KR1020010038081

申请日：2001-06-29

Applicant: 삼성전자주식회사

Inventor： 구형완

IPC: H03M1/66

CPC classification number: H03M1/742 ,  H03M2201/6372 ,  H03M2201/814

Abstract: PURPOSE: A current output type digital/analog converter is provided, which reduces a differential linearity of an output current value by increasing a channel width of a transistor included in a 16 times or 32 times current source. CONSTITUTION: According to a current output type digital/analog converter comprising units outputting current value respectively and being connected to a common port, each unit comprises the first and the second current sources(192,196) outputting an upper data bit group and including a plurality of serially connected transistors, and the third current source(194) outputting a lower data bit group and including at least one transistor. At least one of the transistors of the first and the second current source has a different channel width from other transistors.

Abstract translation: 目的：提供电流输出型数字/模拟转换器，通过增加包含在16倍或32倍电流源中的晶体管的沟道宽度来减小输出电流值的微分线性度。 构成：根据电流输出型数字/模拟转换器，其包括分别输出电流值并连接到公共端口的单元，每个单元包括第一和第二电流源（192,196），其输出上数据位组并且包括多个 串联连接的晶体管，第三电流源（194）输出下部数据位组并且包括至少一个晶体管。 第一和第二电流源的至少一个晶体管具有与其它晶体管不同的沟道宽度。

公开(公告)号：KR1020000072961A

公开(公告)日：2000-12-05

申请号：KR1019990015932

申请日：1999-05-03

Applicant: 삼성전자주식회사

Inventor： 백승범

IPC: H03M1/66

CPC classification number: H03M1/745 ,  H03M2201/6372

Abstract: PURPOSE: A digital-analog converter is provided which minimizes differential non-linearity error and integral non-linearity error. CONSTITUTION: A current segment type digital-analog converter includes a decoder, a selection control circuit, a current source circuit and a current compensation control circuit. The selection control circuit(110) generates signals for selecting current sources according to the output signal of the decoder. A current cell array(120) is configured of LSB binary current cells, MSB segment current cells and switch paris corresponding to the current cells. Odd-numbered switches(S1,S3,S5,S9,Sn-1) among the switch paris are connected to the current compensation control circuit(130) in common. The current compensation control circuit measures current provided by the selected current cells to determine the amount of current to be compensated. The output of the current compensation circuit enters the segment current cells to compensate for current.

Abstract translation: 目的：提供数字模拟转换器，可最大限度地减少差分非线性误差和积分非线性误差。 构成：当前段型数模转换器包括解码器，选择控制电路，电流源电路和电流补偿控制电路。 选择控制电路（110）根据解码器的输出信号产生用于选择电流源的信号。 当前单元阵列（120）由LSB二进制当前单元，MSB段当前单元和与当前单元相对应的开关代码配置。 交换机中的奇数开关（S1，S3，S5，S9，Sn-1）共同地连接到电流补偿控制电路（130）。 电流补偿控制电路测量由所选择的当前单元提供的电流以确定待补偿的电流量。 电流补偿电路的输出进入段电流单元以补偿电流。

公开(公告)号：KR1020140128573A

公开(公告)日：2014-11-06

申请号：KR1020130047103

申请日：2013-04-29

Applicant: 한국과학기술원

Inventor： 류승탁 ,  최영재 ,  김미란 ,  박상훈 ,  김기진 ,  안광호

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M7/165 ,  H03M2201/6107 ,  H03M2201/6372

Abstract: 디지털 아날로그 컨버터의 정적 선형성 향상을 위한 분할 계층적 대칭 스위칭 기법 및 그를 위한 장치에 관한 것이다. 더욱 상세하게는, 시스템 에러의 대칭성을 이용하여 스위칭 순서를 제어하여 시스템 에러의 크기를 줄일 수 있는 디지털 아날로그 컨버터의 정적 선형성 향상을 위한 분할 계층적 대칭 스위칭 기법 및 그를 위한 장치에 관한 것이다.

Abstract translation: 本发明涉及用于静态线性改进的数字模拟转换器的分离式分层对称切换方案及其装置。 更具体地，本发明涉及用于静态线性改进的数字模拟转换器的分离式分层对称切换方案，其通过使用系统误差的对称性并减小系统误差的大小来控制切换顺序及其装置。

公开(公告)号：KR101293057B1

公开(公告)日：2013-08-05

申请号：KR1020120025574

申请日：2012-03-13

Applicant: 동국대학교 산학협력단

Inventor： 송민규 ,  김대윤

IPC: H03M1/12 ,  H04N5/3745

CPC classification number: H03M1/56 ,  H03M1/0607 ,  H03M2201/23 ,  H03M2201/32 ,  H03M2201/615 ,  H03M2201/6372 ,  H04N5/3745

Abstract: PURPOSE: A comparator, an analog-to-digital (A/D) converter, a ramp signal slope compensating circuit, a complementary metal-oxide semiconductor (CMOS) image sensor containing the circuit, and a ramp signal slope compensating method in accordance with the above are provided to prevent the slope ratio of a fine ramp signal to a coarse ramp signal from being distorted due to the slope change of the fine ramp signal and to improve linearity of A/D conversion. CONSTITUTION: An A/D converter (10) includes an amplifier, a comparator (12), a first memory part (16), and a second memory part (18). The amplifier receives a pixel voltage, a reference voltage, a fine ramp voltage, and a coarse ramp voltage. The comparator is equipped with a switch, which is connected between a coarse ramp voltage input terminal receiving coarse ramp voltage input and the amplifier, and a capacitor. One end of the capacitor is connected between the switch and the amplifier, and the other end is connected to a ground voltage. The first memory part stores the most significant bit among 1 least significant bit (LSB) for the coarse ramp voltage. The second memory part stores the least significant bit among 1 LSB for the coarse ramp voltage. [Reference numerals] (12) Comparator; (14) Sink block part; (16) First memory part; (18) Second memory part; (21) Fine ramp generator; (22) Coarse ramp generator; (30) N bit counter

Abstract translation: 目的：比较器，模数（A / D）转换器，斜坡信号斜率补偿电路，含有电路的互补金属氧化物半导体（CMOS）图像传感器，以及根据 提供上述方式以防止精细斜坡信号与粗斜坡信号的斜率比由于精细斜坡信号的斜率变化而失真并提高A / D转换的线性度。 构成：A / D转换器（10）包括放大器，比较器（12），第一存储器部分（16）和第二存储器部分（18）。 放大器接收像素电压，参考电压，精细斜坡电压和粗斜坡电压。 比较器配有开关，连接在接收粗斜坡电压输入的粗斜坡电压输入端子和放大器之间，以及电容器。 电容器的一端连接在开关和放大器之间，另一端连接到接地电压。 第一个存储器部分存储粗斜坡电压的1个最低有效位（LSB）中的最高有效位。 第二存储器部分存储粗略斜坡电压的1 LSB中的最低有效位。 （附图标记）（12）比较器 （14）槽块部分; （16）第一记忆部分; （18）第二记忆部分; （21）细斜坡发生器; （22）粗斜坡发生器; （30）N位计数器

公开(公告)号：KR1020070059857A

公开(公告)日：2007-06-12

申请号：KR1020060050320

申请日：2006-06-05

Applicant: 한국전자통신연구원

Inventor： 김이경 ,  권종기 ,  김종대 ,  조민형 ,  이승철 ,  김규현

IPC: H03M3/04

CPC classification number: H03M3/50 ,  H03M2201/61 ,  H03M2201/6372 ,  H03M2201/8152

Abstract: A multi-bit sigma delta modulator with one DAC capacitor and a DAC(Digital-Analog Converter) for the multi-bit sigma delta modulator are provided to increase the number of output levels of the DAC by expanding the DAC capacitor. A multi-bit sigma delta modulator includes an operation amplifier(21), a sampling capacitor(22), an integration capacitor(23), a DAC capacitor(24), switches(25,26,27), and a switching controller(28). The sampling capacitor(22) is connected between the first switch(26) and an input terminal of the operation amplifier(21). The first switch(26) is connected between the input terminal of the operation amplifier(21) and a ground. The second switch(27) is connected between an input(IN) and the sampling capacitor(22). The integration capacitor(23) connects an output(OUT) and the input terminal of the operation amplifier(21) to form a negative feedback loop. The DAC capacitor(24) is connected between the DAC switch(25) and the input terminal of the operation amplifier(21). The DAC switch(25) connects reference voltages(Vrefp,Vcm,Vrefn) to the DAC capacitor(24) for a DAC of a switched capacitor structure to perform a desired operation. The switching controller(28) controls operation of the DAC switch(25) by generating a control signal according to an ADC output code of a modulator.

Abstract translation: 提供具有一个DAC电容器的多位Σ-Δ调制器和用于多位Σ-Δ调制器的DAC（数模转换器），以通过扩展DAC电容器来增加DAC的输出电平数量。 多位Σ-Δ调制器包括运算放大器（21），采样电容器（22），积分电容器（23），DAC电容器（24），开关（25,26,27）和开关控制器 28）。 采样电容器（22）连接在第一开关（26）和运算放大器（21）的输入端子之间。 第一开关（26）连接在运算放大器（21）的输入端和地之间。 第二开关（27）连接在输入（IN）和采样电容器（22）之间。 积分电容器（23）连接输出（OUT）和运算放大器（21）的输入端，以形成负反馈回路。 DAC电容器（24）连接在DAC开关（25）和运算放大器（21）的输入端子之间。 DAC开关（25）将用于开关电容器结构的DAC的参考电压（Vrefp，Vcm，Vrefn）连接到DAC电容器（24）以执行期望的操作。 开关控制器（28）通过根据调制器的ADC输出代码产生控制信号来控制DAC开关（25）的操作。

公开(公告)号：KR1020070059844A

公开(公告)日：2007-06-12

申请号：KR1020060046037

申请日：2006-05-23

Applicant: 한국전자통신연구원

Inventor： 조민형 ,  권종기 ,  김종대 ,  김귀동

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/0621 ,  H03M1/1023 ,  H03M2201/63 ,  H03M2201/6372

Abstract: A dynamic linearization digital-to-analog converter is provided to obtain high dynamic linearity by dynamically compensating deterioration of linearity due to mismatch caused by spatial arrangement of unit current sources. A dynamic linearization digital-to-analog converter includes a decoder(12), a current switch driver(14), and a random selecting switch(13). The decoder(12) selects a current source(15) from a digital input. The current switch driver(14) drives a current switch of the current source(15). The random selecting switch(13) is located between the decoder(12) and the current switch driver(14), and resets connection between an output of the decoder(12) and an input of the current switch driver(14) randomly every clock.

Abstract translation: 提供动态线性化数模转换器，以通过动态补偿由于单位电流源的空间布置引起的失配引起的线性劣化，以获得高动态线性度。 动态线性化数模转换器包括解码器（12），电流开关驱动器（14）和随机选择开关（13）。 解码器（12）从数字输入端选择电流源（15）。 当前的开关驱动器（14）驱动电流源（15）的电流开关。 随机选择开关（13）位于解码器（12）和电流开关驱动器（14）之间，并且每时钟随机地重置解码器（12）的输出和当前开关驱动器（14）的输入端之间的连接 。

公开(公告)号：KR1020060084119A

公开(公告)日：2006-07-24

申请号：KR1020050004139

申请日：2005-01-17

Applicant: 삼성전자주식회사

Inventor： 남궁윤

IPC: H03M1/10

CPC classification number: H03M1/1038 ,  H03M1/1033 ,  H03M2201/192 ,  H03M2201/20 ,  H03M2201/6164 ,  H03M2201/63 ,  H03M2201/6372

Abstract: 본 발명은 센서에 의해 측정된 물리적 신호의 크기를 원하는 측정값으로 매핑하는 방법에 있어서 물리적 신호의 크기를 디지털 값으로 변환하는 아날로그 디지털 컨버터의 게인 편차에 의한 에러를 보상하는 캘리브레이션 방법에 관한 것이다.
본 발명에 따른 ADC의 캘리브레이션 방법은 ADC를 게인의 크기에 따라 표준의 게인을 가지는 표준 게인 그룹, 표준보다 높은 게인을 가지는 하이 게인 그룹, 그리고 표준보다 낮은 게인을 가지는 로우 게인 그룹들로 분류하는 과정; 상기 분류된 그룹들 각각에 상당하는 변환식들을 설정하는 과정; ADC에 의해 아날로그값을 디지털 값으로 변환하고, 디지털 변환된 값을 ADC가 속한 그룹에 해당하는 변환식에 의해 원하는 측정값으로 매핑하는 과정; 및 매핑된 측정값을 상기 ADC가 속한 그룹을 참조하여 캘리브레이션하는 과정을 포함하는 것을 특징으로 한다.
본 발명에 따른 ADC의 캘리브레이션 방법은 ADC의 게인 편차에 의한 측정값의 오류를 보상함으로써 정확한 측정값을 얻게 하는 효과를 가진다.

公开(公告)号：KR1020020046485A

公开(公告)日：2002-06-21

申请号：KR1020000076681

申请日：2000-12-14

Applicant: 매그나칩 반도체 유한회사

Inventor： 문홍식

IPC: H03M1/76

CPC classification number: H03M1/76 ,  H03M2201/62 ,  H03M2201/6372

Abstract: PURPOSE: A D/A(Digital to Analog) transformer is provided to reduce a linear error due to discordance between resistors and an occupied area by decreasing the number of resistors necessary for generating an analog level in half. CONSTITUTION: A D/A transformer comprises a reference current source(Iref) for deciding a voltage level of resistors(R) arrayed in series, a reference voltage source(Vcom) for supplying a center voltage of an output signal of the D/A transformer, switches(SW1-SW6) for varying a voltage level by changing a flow direction of a current flowing to the arrayed resistors(R), a decoder(10) for selecting an output level by decoding a digital signal, and a buffer(20) for supplying an analog signal by buffering the analog signal selected from the decoder(10).

Abstract translation: 目的：提供D / A（数字到模拟）变压器，通过减少将模拟电平降低一半所需的电阻数量，减少由于电阻和占用区域之间的不一致引起的线性误差。 构成：AD / A变压器包括用于决定串联排列的电阻器（R）的电压电平的参考电流源（Iref），用于提供D / A变压器的输出信号的中心电压的参考电压源（Vcom） 用于通过改变流向阵列电阻器（R）的电流的流动方向来改变电压电平的开关（SW1-SW6），用于通过解码数字信号来选择输出电平的解码器（10）和缓冲器 ），用于通过缓冲从解码器（10）中选择的模拟信号来提供模拟信号。