公开(公告)号：EP4181209A1

公开(公告)日：2023-05-17

申请号：EP22200481.4

申请日：2022-10-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yu, Hong ,  Jain, Vibhor

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/73 ,  H01L29/737 ,  H01L29/735

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor (10) with a collector contact (25) implemented as a back-side contact and methods of manufacture. The structure includes: a lateral bipolar transistor (10) which includes an emitter (20), a base (22) and a collector (18); an emitter contact (30) to the emitter; a base contact (32) to the base; and a collector contact (25) to the collector and extending to an underlying substrate (14) underneath the collector.

公开(公告)号：EP4156289A1

公开(公告)日：2023-03-29

申请号：EP22198490.9

申请日：2022-09-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： YU, Hong ,  JAIN, Vibhor ,  HOLT, Judson R.

IPC: H01L29/737 ,  H01L21/331 ,  H01L29/08

Abstract: A structure comprises: a base region (140) comprising a base layer (105); a buffer layer (108a) positioned laterally immediately adjacent to the base layer; and a collector region (120) comprising a collector layer (109a) positioned laterally immediately adjacent to the buffer layer, wherein the base layer, the buffer layer, and the collector layer comprise different semiconductor materials with different bandgap sizes.

公开(公告)号：EP4550015A1

公开(公告)日：2025-05-07

申请号：EP24170916.1

申请日：2024-04-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： BIAN, Yusheng ,  STRICKER, Andreas D. ,  ABOKETAF, Abdelsalam ,  HOLT, Judson R. ,  DEZFULIAN, Kevin K. ,  GIEWONT, Kenneth J. ,  DERRICKSON, Alexander ,  LEE, Won Suk ,  CHANDRAN, Sujith ,  SPORER, Ryan W. ,  LIN, Teng-Yin

IPC: G02B6/12 ,  G02B6/122

Abstract: Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector that is disposed on a substrate and that includes a light-absorbing layer. The light-absorbing layer includes a sidewall and a notch in the sidewall. The structure further comprises a waveguide core including a section adjacent to the notch in the sidewall of the light-absorbing layer.

公开(公告)号：EP4546404A1

公开(公告)日：2025-04-30

申请号：EP24168608.8

申请日：2024-04-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： BORISOV, Kiril B. ,  ZIER, Manfred Michael ,  BACHER, Alexander S. ,  PRITCHARD, David C. ,  RAMADOUT, Benoit F. C.

IPC: H01L21/74 ,  H01L23/528 ,  H01L23/535

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to buried interconnect structures and methods of manufacture. The structure includes: a semiconductor substrate; a trench isolation structure extending into the semiconductor substrate; and at least one buried interconnect structure in the semiconductor substrate and crossing the trench isolation structure.

公开(公告)号：EP4535658A1

公开(公告)日：2025-04-09

申请号：EP23210094.1

申请日：2023-11-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bellaouar, Abdellatif ,  Syed, Shafiullah

IPC: H03F1/02 ,  H03F1/22 ,  H03F3/195 ,  H03F3/213 ,  H03F3/45

Abstract: A disclosed structure includes a power amplifier and circuitry for implementing a biasing scheme that enables high power operation. The power amplifier includes parallel transistor chains connected to input and output transformers. Each chain includes series-connected first, second, and third n-type field effect transistors (NFETs) having front and back gates. The output transformer receives a variable positive power supply voltage generated using average power tracking. Front and back gates of each third NFET receive a positive bias voltage greater than or equal to the variable positive power supply voltage and a negative bias voltage, respectively. By negative back biasing the third NFETs, threshold voltages thereof are raised so a high positive bias voltage can be applied to the front gates to increase power output without violating reliability specifications. Optionally, by making the negative bias voltage temperature dependent, voltages at source regions of the third NFETs are held constant.

公开(公告)号：EP4535053A1

公开(公告)日：2025-04-09

申请号：EP24168618.7

申请日：2024-04-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dash, Aneesh ,  Rakowski, Michal ,  Chatterjee, Avijit ,  Minasamudram, Rupa Gopinath

IPC: G02B6/293 ,  G02F1/225

Abstract: Structures (10) for an optical switch and methods of forming such structures. The structure (10) comprises a first waveguide core (14) including a first portion and a second portion, a second waveguide core (12) including a first portion and a second portion, a ring resonator (18) having a first portion adjacent to the first portion of the first waveguide core (14) and a second portion adjacent to the first portion of the second waveguide core (12), and an optical coupler (20) coupled to the second portion of first waveguide core (14) and the second portion of the second waveguide core (12). The first portion of the ring resonator (18) is spaced from the first portion of the first waveguide core (14) by a first gap over a first light coupling region, and the second portion of the ring resonator (18) is spaced from the first portion of the second waveguide core (12) by a second gap over a second light coupling region.

公开(公告)号：EP4498096A1

公开(公告)日：2025-01-29

申请号：EP24152754.8

申请日：2024-01-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Kim, Jae Hoon

IPC: G01R1/04 ,  G01R31/28

Abstract: A test tray system for electronics, like photonics integrated circuit (PIC) structures, and a related method are disclosed. The test tray system includes at least one test tray. Each test tray includes a first section exposing a first electrical component to a high temperature, and a second section covered by a thermal protection element configured to prevent a second component from being exposed to the high temperature at the same time that the first electrical component is being exposed to the high temperature. The test tray system allows testing of the first component at a high temperature, e.g., 125°C, while protecting the second component from the high temperatures.

公开(公告)号：EP4379811A3

公开(公告)日：2024-09-04

申请号：EP23199260.3

申请日：2023-09-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： SHARMA, Santosh ,  KRISHNASAMY, Rajendran ,  KANTAROVSKY, Johnatan A.

IPC: H01L29/778 ,  H01L21/337 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/1066 ,  H01L29/404 ,  H01L29/0657 ,  H01L29/66462

Abstract: Semiconductor structures and, more particularly, a high-electron-mobility transistor and methods of manufacture thereof are disclosed. The structure includes: a gate structure (18, 22, 28); and a channel region (14, 16) under the gate structure, the channel region having a first portion including a first thickness and a second portion having a second thickness greater than the first thickness, the second portion being positioned remotely from the gate structure.

公开(公告)号：EP4421849A1

公开(公告)日：2024-08-28

申请号：EP23201754.1

申请日：2023-10-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhao, Zhixing ,  Kleimaier, Dominik M. ,  Duenkel, Stefan

IPC: H01L21/28 ,  G11C11/22 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H10B51/30

CPC classification number: H10B51/30 ,  H01L29/516 ,  H01L29/513 ,  H01L29/42368 ,  H01L29/6684 ,  H01L29/7833 ,  H01L29/78391 ,  H01L29/40111 ,  G11C11/223 ,  G11C11/5657 ,  G11C11/2273 ,  G11C11/2275

Abstract: A ferroelectric memory device (100) includes a substrate (110) including a source region (120) and a drain region (130), and a gate structure (140) disposed over the substrate. The gate structure includes a gate electrode (146) including a plurality of electrode portions (146', 146'') arranged in a first direction parallel to a top surface of the substrate, an oxide layer (142) including a plurality of oxide portions (142', 142'') corresponding respectively to the plurality of electrode portions, and a ferroelectric layer (144) disposed between the gate electrode and the oxide layer along a second direction perpendicular to the first direction and including a plurality of ferroelectric portions (144', 144'') corresponding respectively to the plurality of oxide portions. A least one of the plurality of oxide portions and at least one of the plurality of ferroelectric portions have different thicknesses along the second direction.

公开(公告)号：EP4418320A1

公开(公告)日：2024-08-21

申请号：EP23191650.3

申请日：2023-08-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pritchard, David Charles ,  Mazza, James P. ,  Jain, Navneet K. ,  Yu, Hong

IPC: H01L27/02 ,  H01L27/118 ,  H01L21/8238

CPC classification number: H01L27/0207 ,  H01L27/11807 ,  H01L2027/1186620130101 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823871 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092

Abstract: A standard cell or integrated circuit (IC) structure includes a substrate including a first active region and a second active region. A first gate electrode is over the first active region; and a second gate electrode over the second active region. A trench isolation electrically isolates the first active region and the first gate electrode from the second active region and the second gate electrode. First ends of the first active region and the first gate electrode abut a first sidewall of the trench isolation and first ends of the second active region and the second gate electrode abut a second, opposing sidewall of the trench isolation. A conductive strap extends over an upper end of the trench isolation and electrically couples the first gate electrode and the second gate electrode.