公开(公告)号：AU2002343408A1

公开(公告)日：2003-04-01

申请号：AU2002343408

申请日：2002-09-17

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK

IPC: H01L29/41 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119 ,  H01L31/113

Abstract: A wrapped-gate transistor includes a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer is formed on the substrate. A gate electrode is formed on the gate dielectric layer to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric therebetween. The substrate is a silicon island formed on an insulation layer of an SOI (silicon-on-insulator) substrate or on a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the "body-to-source" voltage.

公开(公告)号：DE112011100948T5

公开(公告)日：2013-01-24

申请号：DE112011100948

申请日：2011-03-31

Applicant: IBM

Inventor： BOOTH ROGER A ,  KANGGUO CHENG ,  PEI CHENGWEN ,  FURUKAWA TOSHIHARU

IPC: H01L27/06 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L29/94

Abstract: Eine integrierte Schaltung mit FinFETs (60a, b) und einem Metall-Isolator-Metall(MIM)-Fin-Kondensator (65) und Fertigungsverfahren werden offenbart. Das Verfahren beinhaltet das Bilden eines ersten FinFET (60a), der ein erstes Dielektrikum (25) und einen ersten Leiter (30) umfasst; das Bilden eines zweiten FinFET (60b), der ein zweites Dielektrikum (40) und einen zweiten Leiter (45) umfasst; und das Bilden eines Fin-Kondensators (65), der den ersten Leiter (25), das zweite Dielektrikum (40) und den zweiten Leiter (45) umfasst.

公开(公告)号：AT552533T

公开(公告)日：2012-04-15

申请号：AT06793213

申请日：2006-09-05

Applicant: IBM

Inventor： HOLMES STEVEN ,  FURUKAWA TOSHIHARU ,  KOBURGER CHARLES ,  MOUMEN NAIM

IPC: G03F7/20 ,  G03F7/11

Abstract: An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

公开(公告)号：AT504946T

公开(公告)日：2011-04-15

申请号：AT05707994

申请日：2005-02-10

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  KOBURGER CHARLES ,  MITCHELL PETER ,  NESBIT LARRY

IPC: H01L51/05 ,  G11C13/02 ,  H01L21/335 ,  H01L21/336 ,  H01L27/28 ,  H01L29/06 ,  H01L29/12 ,  H01L29/772 ,  H01L51/30 ,  H01L51/40

Abstract: Carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, device structures, and arrays of device structures. A stacked device structure includes a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The gate electrode has a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

公开(公告)号：DE60233241D1

公开(公告)日：2009-09-17

申请号：DE60233241

申请日：2002-08-29

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  LEAS JAMES M ,  MA WILLIAM H ,  RABIDOUX PAUL A

IPC: H01L29/76 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

Abstract: A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

公开(公告)号：DE602005005302T2

公开(公告)日：2009-03-12

申请号：DE602005005302

申请日：2005-01-13

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV ,  MITCHELL PETER ,  NESBIT LARRY ALAN

IPC: H01L51/30 ,  H01L21/78 ,  H01L27/28

Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

公开(公告)号：DE602005005302D1

公开(公告)日：2008-04-24

申请号：DE602005005302

申请日：2005-01-13

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV ,  MITCHELL PETER ,  NESBIT LARRY ALAN

IPC: H01L51/30 ,  H01L21/78 ,  H01L27/28

Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

公开(公告)号：MY126185A

公开(公告)日：2006-09-29

申请号：MYPI20023100

申请日：2002-08-22

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK A

IPC: H01L29/41 ,  H01L21/336 ,  H01L29/94 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L31/113

Abstract: A WRAPPED-GATE TRANSISTOR INCLUDES A SUBSTRATE HAVING AN UPPER SURFACE AND FIRST AND SECOND SIDE SURFACES OPPOSING TO EACH OTHER.SOURCE AND DRAIN REGIONS (28) ARE FORMED IN THE SUBSTRATE WITH A CHANNEL REGION THEREBETWEEN. THE CHANNEL REGION EXTENDS FROM THE FIRST SIDE SURFACE TO THE SECOND SIDE SURFACES OF THE SUBSTRATE. A GATE DIELECTRIC LAYER (40) IS FORMED ON THE SUBSTRATE. A GATE ELECTRODE (42) IS FORMED ON THE GATE DIELECTRIC LAYER TO COVER THE CHANNEL REGION FROM THE UPPER SURFACE AND THE FIRST AND SECOND SIDE SURFACES WITH THE GATE DIELECTRIC THEREBETWEEN. THE SUBSTRATE IS A SILICON ISLAND FORMED ON AN INSULATION LAYER OF AN SOI (SILICON-ON-INSULATOR) SUBSTRATE OR ON A CONVENTIONAL NON-SOI SUBSTRATE, AND HAS FOUR SIDE SURFACES INCLUDING THE FIRST AND SECOND SIDE SURFACES. THE SOURCE AND DRAIN REGIONS ARE FORMED ON THE PORTIONS OF THE SUBSTRATE ADJOINING THE THIRD AND FOURTH SIDE SURFACES WHICH ARE PERPENDICULAR TO THE FIRST AND SECOND SIDE SURFACES. THE WRAPPEDGATE STRUCTURE PROVIDES A BETTER AND QUICKER POTENTIAL CONTROL WITHIN THE CHANNEL AREA, WHICH YIELDS STEEP SUB-THRESHOLD SLOPE AND LOW SENSITIVITY TO THE "BODY-TO-SOURCE" VOLTAGE.(FIG 18A)

公开(公告)号：MY117201A

公开(公告)日：2004-05-31

申请号：MYPI9904530

申请日：1999-10-20

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  RABIDOUX PAUL A

IPC: G03C5/00 ,  H01L21/28 ,  H01L21/027 ,  H01L21/302 ,  H01L21/32 ,  H01L21/60 ,  H01L21/768

Abstract: A METHOD FOR FORMING CONTACTS ON AN INTEGRATED CIRCUIT THAT ARE SELF-ALIGNED WITH THE WIRING PATTERNS OF THE INTEGRATED CIRCUIT. IN THE METHOD A THICKER LOWER LAYER (12) OF A FIRST MATERIAL AND A THINNER UPPER LAYER (14) OF A SECOND MATERIAL ARE FORMED ON A SUBSTRATE (10). THE FEATURES OF THE METAL WIRING IS PATTERNED FIRST ON THE UPPER LAYER. THE WIRING PATTERN TRENCHES (20) ARE ETCHED THROUGH THE THINNER SURFACE LAYER, AND PARTIALLY THROUGH THE SECOND, THICKER LAYER. AFTER THE WIRING PATTERN IS ETCHED, THE CONTACTS FOR THE WIRING LAYER ARE PRINTED AS LINE/SPACE PATTERNS WHICH INTERSECT THE WIRING PATTERN. THE CONTACT PATTERN IS ETCHED INTO THE LOWER, THICKER LAYER WITH AN ETCH PROCESS THAT IS SELECTIVE TO THE UPPER THINNER LAYER. THE CONTACT IS ONLY FOFFI1ED AT THE INTERSECTION POINT OF THE WIRING IMAGE WITH THE CONTACT IMAGE, THEREFORE THE CONTACT IS SELF-ALIGNED TO THE METAL (24).

公开(公告)号：GB2494338A

公开(公告)日：2013-03-06

申请号：GB201221985

申请日：2011-03-31

Applicant: IBM

Inventor： BOOTH ROGER A ,  KANGGUO CHENG ,  PEI CHENGWEN ,  FURUKAWA TOSHIHARU

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L29/94

Abstract: An integrated circuit having finFETs(60a,b) and a metal-insulator-metal (MIM) fin capacitor (65) and methods of manufacture are disclosed. A method includes forming a first finFET (60a) comprising a first dielectric (25) and a first conductor (30); forming a second finFET (60b) comprising a second dielectric (40) and a second conductor (45); and forming a fin capacitor (65) comprising the first conductor (25), the second dielectric (40), and the second conductor (45).