公开(公告)号：JP2000012801A

公开(公告)日：2000-01-14

申请号：JP14714699

申请日：1999-05-26

Applicant: IBM ,  SIEMENS AG

Inventor： ECONOMIKOS LAERTIS ,  GRUENING ULRIKE ,  HO HERBERT L ,  RADENS CARL J ,  JAMMY RAGARAO ,  HOEPFNER JOACHIM ,  SHEN HUA

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligned collar and a buried plate while forming a reliable node dielectrics on the collar without requiring a plurality of independent trench recesses for forming the buried plate and the collar. SOLUTION: Etching for a trench is made within a surface of a semiconductor substrate 10 and a dielectric material layer is formed on a side wall 12 of the trench. The dielectric material layer is partially eliminated to expose a lower base region of the upper part of the trench side wall 12. After that an oxide layer is made to grow on the upper part of the side wall 12. The dielectric layer is eliminated from a remaining part of the side wall 12 and a buried plate 17 is formed by doping. The dielectric layer includes the upper part of the collar and a node, (i,e, the trench wall at a portion of the buried plate 17) and is provided for the trench wall. An inner electrode 19 is formed at the inner part of the trench.

公开(公告)号：JP2003133317A

公开(公告)日：2003-05-09

申请号：JP2002193642

申请日：2002-07-02

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHEW ,  RADENS CARL J ,  WANG LI-KONG ,  WONG KEITH KWONG HON

IPC: G03F7/40 ,  H01B13/00 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/52 ,  H05K3/02

Abstract: PROBLEM TO BE SOLVED: To provide a more simplified substitutional method of the conventional damascene approach. SOLUTION: The cloisonne approach includes a step of coating a semiconductor substrate with a photosensitive polymer, such as pyrrole having a silver salt, aniline, etc. A conductive polymer is exposed to a wet developing solution, by using standard photolithography and the resists developing method and only conductive polymer wires are left on a substrate by removing part of the exposed conductive polymer region. Then an insulating dielectric layer is adhered to the whole structure, and conductive polymer wires are produced by planarizing an insulator by the chemical mechanical polishing (CMP). Another embodiment of this invention includes a method and structure for a self- planarizing interconnecting material containing the conductive polymer. Consequently, the number of treating steps can be reduced, as compared with the conventional technology.

公开(公告)号：JP2002305287A

公开(公告)日：2002-10-18

申请号：JP2002016927

申请日：2002-01-25

Applicant: IBM

Inventor： MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal-oxide film semiconductor integrated circuit which contains a notched gate in a support device region, and to provide a method of forming the integrated circuit. SOLUTION: A gate stack 16 is formed on a substrate, a patterned mask 24 is formed on the gate stack, the stack gate is etched by using the mask, and rather than the entire part but a part of a gate conductor is removed. A gap-filling film 28 is formed on the whole face, and the gap-filling film is removed in such a way that the gap filling film is left between masked gate stacks in an array device region. A spacer is formed on the exposed sidewall of the masked gate stack, and the exposed gate conductor inside the array device region and inside the support device region is removed. An undercut is formed in the lower exposed part of the remaining gate conductor. The remaining gap filling film is removed from the masked protective gate stack inside the array device region.

公开(公告)号：JP2002222873A

公开(公告)日：2002-08-09

申请号：JP2001388866

申请日：2001-12-21

Applicant: IBM

Inventor： RAMACHANDORA DEIVAKARUNI ,  LEE HEON ,  MANDELMAN JACK A ,  RADENS CARL J ,  SIM JAI-HOON

IPC: H01L21/8242 ,  H01L21/336 ,  H01L27/108 ,  H01L29/772

Abstract: PROBLEM TO BE SOLVED: To provide an improved method of forming a vertical MOSFET structure. SOLUTION: A method of forming a semiconductor memory cell array structure comprises a process of providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer 22 planarized up to the top surface of a trench top oxide 24 on a silicon substrate, a process of forming a recess 39 in the gate conductor layer below the top surface of the silicon substrate, a process of forming doping pockets 46 in an array P well 32 by implanting N-type dopant species through the recess at an angle, a process of forming spacers 44 on the side wall of the recess by depositing an oxide layer in the recess and then etching the oxide layer, and a process of depositing a gate conductor material in the recess and then planarizing the gate conductor material up to the top surface of the trench top oxide.

公开(公告)号：JP2001007223A

公开(公告)日：2001-01-12

申请号：JP2000160941

申请日：2000-05-30

Applicant: IBM

Inventor： JEFFREY P GANBINO ,  LEWIS L SUU ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a dual work function gate conductor having a self-aligned insulating cap, and a method for forming the dual work function gate conductor. SOLUTION: Two diffusion regions 36 are formed on a substrate 20, and gate stacks 33 and 34 are formed on the substrate 20 between these regions 36. The stacks 33 and 34 have a gate insulating layer 24, and polysilicon layers 26 and 26a on the layer 24, respectively. The layers 26 and 26a are n-type doped and remain intrinsic. A barrier layer 28 is formed on each of the layers 26 and 26a. A dopant source 30 is formed on the layer 28 for both stacks 33 and 34. The layer 28 has a p-type dopant. The stacks 33 and 34 are covered with an insulating cap 32 so that diffusion contacts can be formed on the gates in a borderless manner. When to start activating the source 30 for doping the layers 26 and 26a can be postponed until the desired timing.

公开(公告)号：JP2000323684A

公开(公告)日：2000-11-24

申请号：JP2000085406

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  HALLE SCOTT ,  RADENS CARL J ,  JEFFREY J WERSER ,  BEINTNER JOCHEN ,  MANDELMAN JACK A ,  WITTMANN JUERGEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To form a trench capacitor in a semiconductor body. SOLUTION: A trench capacitor 10 and a MOS transistor 9 are provided in a substrate 16 to form a cell 8 of the DRAM, and the cell 8 is separated from adjacent cells by an STI region 28. The capacitor 10 is composed of an insulator 14 enveloping the trench and a first electrode 24 filled with polysilicon 12, is connected to the drain portion 72 through a buried electrode 22, and is insulated from a gate electrode 20 by a dielectric 23. A second electrode 25 is formed in its bottom portion through an insulator 14. A transistor 9 has N-type drain 72 and source 71 in an upper active region 11 of the substrate 16 and operates with a p well as channel.

公开(公告)号：JP2000269464A

公开(公告)日：2000-09-29

申请号：JP2000077068

申请日：2000-03-17

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： PARK YOUNG-JIN ,  RADENS CARL J ,  GERHARD KUNKEL

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To reduce an interference action between a buried strap and an access transistor channel of a semiconductor memory, by making a distance between a gate and the side of a trench larger than the minimum feature size. SOLUTION: A trench 102 forms an angle A at 0 degree to 45 degrees to a word line 104, and the angled portion 108 of an active area 106 forms a herringbone pattern to effectively lay out components such as the trench 102 and a contact 116. A portion 110 of the active area 106 is elongated to a value larger than feature size F to increase an average distance to reduce a dopant interference between the buried strap of the trench 102 and the word line 104. Therefore, this realizes a longer distance between the trench 102 and the bit line contact 116.

公开(公告)号：JP2000091525A

公开(公告)日：2000-03-31

申请号：JP25944099

申请日：1999-09-13

Applicant: IBM

Inventor： JAMMY RAJARAO ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor memory structure, especially a deep trench semiconductor memory device for which a temperature sensitive high dielectric constant material is taken inside the storage node of a capacitor. SOLUTION: In this manufacturing method, after shallow trench separation at high temperature and processing a gate conductor, a deep trench storage capacitor is manufactured. With the manufacturing method, a temperature sensitive high dielectric constant material can be taken into a capacitor structure without causing decomposition of the material. Furthermore, the manufacturing method limits the spread of a buried strap outward diffused part 44, and thus the electric characteristics of an array MOSFET are improved.

公开(公告)号：JP2005197743A

公开(公告)日：2005-07-21

申请号：JP2005000921

申请日：2005-01-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CASEY JON A ,  FERRANTE WILLIAM J ,  KIEWRA EDWARD W ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/28 ,  G01K7/22 ,  H01C7/00 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04

CPC classification number: H01L21/76895 ,  G01K7/226 ,  H01C7/006 ,  H01L21/76224 ,  H01L21/76838

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for forming a thermistor.
SOLUTION: An isolation region is formed in a substrate including at least an upper side layer of a single crystal semiconductor. A salicide precursor layer is formed on the isolation region and the upper side layer. Then, reaction of the salicide precursor and the upper side layer is performed and a salicide which is self-aligned to the upper side layer is formed. Finally, no reaction portion of the salicide precursor is removed, while preserving the portion of the salicide precursor on the isolation region as the main body of the thermistor. In alternative method, an integrated circuit thermistor is formed from a thermistor material region in an embossed region of interlayer dielectric (ILD).
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于形成热敏电阻的结构和方法。 解决方案：在至少包含单晶半导体的上侧层的衬底中形成隔离区。 在隔离区域和上侧层上形成自对准硅化物前体层。 然后，进行自对准硅化物前体与上侧层的反应，形成与上侧层自对准的自对准硅化物。 最后，除去自杀化合物前体的反应部分，同时保留作为热敏电阻的主体的隔离区上的部分自杀化合物前体。 在替代方法中，集成电路热敏电阻由层间电介质（ILD）的压花区域中的热敏电阻材料区域形成。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004214627A

公开(公告)日：2004-07-29

申请号：JP2003396333

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  DOKUMACI OMER H ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/28114 ,  H01L21/26586 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665

Abstract: PROBLEM TO BE SOLVED: To provide an FET device in which the gate activity, line resistance and S/D extension resistance are improved. SOLUTION: A method for manufacturing a semiconductor transistor device is provided with following steps: a semiconductor substrate is formed; the semiconductor substrate has a gate dielectric layer on its surface; lower gate electrode structure is formed on the surface of the gate dielectric layer and the lower gate electrode structure has a low gate upper surface; a planarized layer is formed on the gate dielectric layer so that the upper part of the lower gate electrode structure is left in an exposed state; upper gate structure is formed on the lower gate electrode structure to form a T-type gate electrode; the lower surface of the upper gate structure and the vertical sidewall of the gate electrode are exposed; the planarized layer is removed; a source/drain extension is formed in the substrate protected from a short channel effect; a sidewall spacer is formed adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewall of the T-type gate electrode. A source/drain region is formed in the substrate. A silicide layer is formed on the upper part of the T-type gate electrode and the upper part of the source/drain region. COPYRIGHT: (C)2004,JPO&NCIPI