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    31.
    发明专利
    未知

    公开(公告)号：DE10392127T5

    公开(公告)日：2004-07-29

    申请号：DE10392127

    申请日：2003-03-13

    Applicant: INTEL CORP

    Inventor： HAMMARLUND PER ,  VENKATRAMAN K S ,  BAKTHA ARAVINDH ,  UPTON MICHAEL

    IPC: G06F12/00 ,  G06F12/08

    Abstract: A context identifier is used in a cache memory apparatus. The context identifier may be written into the tag of a cache line or may be written as an addition to the tag of a cache line, during cache write operation. During a cache read operation, the context identifier of as issued instruction may be compared with the context identifier in the cache line's tag. The cache line's data block may be transferred if the context identifiers and the tags match.

    USE OF A CONTEXT IDENTIFIER IN CACHE MEMORY
    32.
    发明专利
    USE OF A CONTEXT IDENTIFIER IN CACHE MEMORY 未知

    公开(公告)号：AU2003214148A1

    公开(公告)日：2003-10-13

    申请号：AU2003214148

    申请日：2003-03-13

    Applicant: INTEL CORP

    Inventor： HAMMARLUND PER ,  VENKATRAMAN K S ,  BAKTHA ARAVINDH ,  UPTON MICHAEL

    IPC: G06F12/00 ,  G06F12/08

    Abstract: A context identifier is used in a cache memory apparatus. The context identifier may be written into the tag of a cache line or may be written as an addition to the tag of a cache line, during cache write operation. During a cache read operation, the context identifier of as issued instruction may be compared with the context identifier in the cache line's tag. The cache line's data block may be transferred if the context identifiers and the tags match.

    35.
    发明专利
    未知

    公开(公告)号：DE112006000807T5

    公开(公告)日：2008-01-31

    申请号：DE112006000807

    申请日：2006-04-05

    Applicant: INTEL CORP

    Inventor： WANG HONG ,  CHINYA GAUTHAM ,  HANKINS RICHARD ,  RAKVIC RYAN ,  SHEN JOHN ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  HAMMARLUND PER ,  ZOU XIANG ,  BRANDT JASON ,  SETHI PRASHANT ,  REID JOHN ,  POULSEN DAVID ,  RODGERS SCOTT ,  CARMEAN DOUGLAS ,  PATEL BAIJU ,  SHAH SANJIV ,  HELD JAMES ,  ABEL JAMES

    IPC: G06F9/38

    Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

    Synchronisierung der Unterbrechungsverarbeitung zur Verringerung des Stromverbrauchs
    39.
    发明专利
    Synchronisierung der Unterbrechungsverarbeitung zur Verringerung des Stromverbrauchs 未知

    公开(公告)号：DE112014006501T5

    公开(公告)日：2017-01-05

    申请号：DE112014006501

    申请日：2014-03-24

    Applicant: INTEL CORP

    Inventor： LOH THIAM WAH ,  CHINYA GAUTHAM N ,  HAMMARLUND PER ,  FORTAS REZA ,  WANG HONG ,  SUN HUAJIN

    IPC: G06F13/24

    Abstract: Es wird ein Prozessor offenbart, der wenigstens einen Kern, einschließlich eines ersten Kerns, und eine Unterbrechungsverzögerungslogik umfasst. Die Unterbrechungsverzögerungslogik soll eine erste Unterbrechung zu einer ersten Zeit empfangen und die erste Unterbrechung vor einer Verarbeitung um eine erste Zeitverzögerung verzögern, die zur ersten Zeit beginnt, es sei denn, dass die erste Unterbrechung zu einer zweiten Zeit anhängig ist, wenn eine zweite Unterbrechung durch den ersten Kern verarbeitet wird. Falls die erste Unterbrechung zur zweiten Zeit anhängig ist, soll die Unterbrechungsverzögerungslogik den ersten Kern anweisen, vor Abschluss der ersten Zeitverzögerung mit der Verarbeitung der ersten Unterbrechung zu beginnen. Andere Ausführungsformen werden offenbart und beansprucht.

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