公开(公告)号：JPH11168369A

公开(公告)日：1999-06-22

申请号：JP19477998

申请日：1998-07-09

Applicant: ST MICROELECTRONICS SRL

Inventor： GENOVA ANGELO ,  CANTONE GIUSEPPE ,  GARIBOLDI ROBERTO

IPC: H03K5/08 ,  G05F3/26 ,  H03K17/16

Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive integrated device of relatively simple and compact constitution without receiving interference at the time of switching. SOLUTION: In this integrated device 105 for a switching system provided with a control means 110 for generating switching control signals, a reference means 120 for generating a reference amount Qref and a means 110 for using the reference amount, the means 130 for storing the reference amount, a switch means 122 for connecting the reference means 120 to a using means 110 and a storage means 130 so as to supply the reference amount Qref in a first operation state and interrupting the reference means 120 from the using means 110, connecting the storage means 130 to the using means 110 and supplying the stored reference amount Qref in a second operation state and a filter means 135 for maintaining the switch means 122 in the second operation sate during a filtering period corresponding to the switching of control signals Sh are provided.

公开(公告)号：JPH11150210A

公开(公告)日：1999-06-02

申请号：JP25481698

申请日：1998-09-09

Applicant: ST MICROELECTRONICS SRL

Inventor： TONDELLI FULVIO SILVIO ,  CIGADA ANDREA GIOVANNI

IPC: B23K3/06 ,  H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To provide a ball aligning system which is capable of realizing a complete array alignment, when balls are dropped from an aligning grid, taking advantage not of vacuum but of free fall. SOLUTION: This system includes first and second plates 1 and 2 moving relative to each other and a filling means 4 movable along the top surface of the plate 1 with the bottom surface of the means 4 contacted with the top surface of the plate 1. The plates 1 and 2 have holed regions 1a and 2a having a ball array corresponding to a ball aligned state on a ball grid array(BGA) device respectively. Since balls in the respective holed regions 1a and 2a are mutually shifted, the balls received in the holes of the plate 1 can be moved through the holes of the plate 2 for falling. The filling means 4 is a container which stocks therein a large number of balls, and which can be moved between the holed region 1a of the plate 1 and a region thereof, other than the holed region 1a. When the means is moved up to the holed region 1a, the means supplies the balls into the respective holes of the holed regions.

公开(公告)号：JPH11122978A

公开(公告)日：1999-04-30

申请号：JP22277198

申请日：1998-08-06

Applicant: ST MICROELECTRONICS SRL

Inventor： GALBIATI EZIO ,  BOSCOLO MICHELE ,  BERTOLINI LUCA

IPC: H02P6/08 ,  H02P6/28 ,  H02P6/18

Abstract: PROBLEM TO BE SOLVED: To control currents of respective windings individually by a method wherein the signals of two detection resistors are compared with a same reference signal to generate logic triggers and signals generated by monostable multivibrator in accordance with the logic triggers, and signals generated by phase switching are supplied to synthetic logic gates which output signals for driving respective half bridges. SOLUTION: A current which flows through a winding A is supplied by turning on transistors T1A and T4A. If the voltage drop of a detection resistor RS2 exceeds a control voltage, the output of a comparator COMP2 triggers a monostable multivibrator ONE2 to change its output to a logic value 1 for a required period. Since an Ina signal and the output signal of the monostable multivibrator ONE2 after the OR process change a gate output OR-a (= drive signal INa) to a logic value 1, the MOS transistor T4A is turned off and a MOS transistor T3A is turned on. Then, the MOS transistors T1A and T4A are turned on to start the increase of a current in the phase winding A. If the voltage drop of the detection resistor RS2 exceeds the control voltage, this cycle is repeated.

公开(公告)号：JPH1187491A

公开(公告)日：1999-03-30

申请号：JP18839898

申请日：1998-07-03

Applicant: ST MICROELECTRONICS SRL

Inventor： QUEIROLO GIUSEPPE ,  OTTAVIANI GIAMPIERO ,  CEROFOLINI GIANFRANCO

IPC: H01L21/302 ,  H01L21/265 ,  H01L21/301 ,  H01L21/304 ,  H01L21/306 ,  H01L21/76

Abstract: PROBLEM TO BE SOLVED: To prevent an interlattice defect formed due to impact from being shifted by keeping the temperature of a crystalline target at a low level when ions are implanted at atomic weight and kinetic energy suitable for rendering the crystal amorphous up to a design depth within a range defined by an ion implantation mask. SOLUTION: When a crystal is a single crystal silicon substrate, the substrate is kept at -196 deg.C (boiling point of nitrogen), for example, and ions are implanted accurately up to a design depth corresponding to the kinetic energy of accelerating ion. Consequently, a crystal matrix is rendered amorphous through the majority shift mechanism of atom in a crystal lattice to be implanted. Since low temperature is kept in order to prevent diffusion of point defect occurring in a solid due to impact, the implanted ions are prevented from being diffused into an adjacent crystal lattice. Consequently, a spatial distribution of templanted ions characteristic of an isolation step face occurring simultaneously on both the side wall and the bottom face at an amorphous part can be attained.

公开(公告)号：JPH1168531A

公开(公告)日：1999-03-09

申请号：JP17718598

申请日：1998-06-24

Applicant: ST MICROELECTRONICS SRL

Inventor： TARANTOLA MARIO ,  CANTONE GIUSEPPE ,  GENOVA ANGELO ,  GARIBOLDI ROBERTO

IPC: H03K17/06 ,  H03K17/0812 ,  H03K17/16

Abstract: PROBLEM TO BE SOLVED: To surely control a gate voltage so that an LDMOS transistor can not be switched on undesiredly by providing a 2nd inverter provided with an input end, to which a 2nd logical signal is inputted and an output end which is connected to a gate node of the LDMOS transistor. SOLUTION: In a pMOS transistor M1, its source is connected to the cathode of a diode D1 and to a charging terminal of a bootstrap capacitor Cp, also its drain is connected to the drain of an nMOS transistor M2 and to the gate of an LDMOS integrated transistor LD. The source of the transistor M2 is connected to an output node A of a control inverter 101 and to the other terminal of the condenser Cp. Then gates of the transistors M1 and M2 are controlled by a logical signal UVLOb and prevent the transistor LD from being turned on accidentally.

公开(公告)号：JPH10303311A

公开(公告)日：1998-11-13

申请号：JP30446697

申请日：1997-11-06

Applicant: ST MICROELECTRONICS SRL

Inventor： GHILARDELLI ANDREA ,  MULATTI JACOPO ,  BRANCHETTI MAURIZIO

IPC: H01L21/8247 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/788 ,  H01L29/792 ,  H02M3/07

Abstract: PROBLEM TO BE SOLVED: To improve efficiency of an electric charge pump by providing each stage of the second group with a joint diode comprising a first electrode connected to an input terminal and a second electrode connected to an output terminal and a second capacitor comprising a first polar plate connected to an output terminal and a second polar plate driven by a digital signal. SOLUTION: Between an output terminal O and an input terminal of an electric charge pump connected to a ground, four stages S1, S2, S3', and S4' are connected in series. Then, with a first group stage as S1 and S2 while a second group stage S3' and S4', a joint diode D comprising a first electrode connected to an input terminal of the second group S3' and a second electrode connected to an output terminal of the S3' is provided, and a second capacitor CL' comprising a first polar plate connected to the output terminal of the S3' and S4' and a second polar plate driven by respective phase signals B' and D' is provided.

公开(公告)号：JPH10302479A

公开(公告)日：1998-11-13

申请号：JP8093998

申请日：1998-03-27

Applicant: ST MICROELECTRONICS SRL

Inventor： BARONI ANDREA ,  RIMONDI DANILO ,  TALIERCIO MICHELE ,  TORELLI COSIMO

IPC: G11C11/41 ,  G11C7/14 ,  G11C11/413 ,  G11C11/419

Abstract: PROBLEM TO BE SOLVED: To reduce current consumption in the write mode by installing a dummy memory train roughly the same as the memory cell to monitor the switching time of the dummy memory and selecting the short time alone strictly required for the operation that the desired line to be programmed switches the memory cell to the desired state. SOLUTION: The device is provided with a memory cell 2, a dummy memory train DC(DMCD0-DMCn) roughly the same as the memory cell and plural gates RD1-RDn which transfer the selected output of the line decoder 3 to the lines. The pre-charge control means 4' pre-charges the dummy train DC to the first logic state when the line is not selected. The detecting means DET1 detects the state where the dummy train DC is discharged from the pre-charge potential to the programming potential by the programming means which makes the dummy train DC correspond to the second logic state contrary to the first one to enable plural gates RD1-RDn and disable them after transferring to the second logic state.

公开(公告)号：JP2791288B2

公开(公告)日：1998-08-27

申请号：JP2943995

申请日：1995-02-17

Applicant: ST MICROELECTRONICS SRL

Inventor： GOLLA CARLA MARIA ,  MACCARRONE MARCO

IPC: G11C29/00 ,  G11C29/04

公开(公告)号：JP2746545B2

公开(公告)日：1998-05-06

申请号：JP8709695

申请日：1995-04-12

Applicant: ST MICROELECTRONICS SRL

Inventor： PALARA SERGIO

IPC: H05B41/24 ,  H02M1/08 ,  H02M7/537 ,  H03K17/30 ,  H03K17/567

公开(公告)号：JP2733030B2

公开(公告)日：1998-03-30

申请号：JP32565494

申请日：1994-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  CASAGRANDE GIULIO

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30