公开(公告)号：DE102005057788A1

公开(公告)日：2007-06-06

申请号：DE102005057788

申请日：2005-12-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

IPC: G11C7/06 ,  G11C11/409 ,  H01L27/108 ,  H03F3/183

Abstract: The memory circuit includes a bit line pair (5, 6), a memory cell (2) with a memory capacitance (3) and a selection transistor (4). When activated, this (4) connects the memory capacitance to one of the bit lines, establishing a charge difference between them (5, 6). The read-out amplifier (10) has one or more transistors (11, 2, 13, 14) amplifying the charge difference. A controller (15) applies a potential to a substrate connection of the transistors (11-14); this potential is a function of the operating state of the memory circuit. The controller applies a first or second potential to the substrate, in accordance with the operating state. The read-out amplifier is activated, to apply a high potential to one bit line, and a low potential to the other. The controller is designed to apply an intermediate potential to the substrate of the transistors, at least with the read-out amplifier inactivated. This potential lies between the low and high potentials on the bit lines. It is selected such that the transistor leakage current does not exceed a given threshold, with the read-out amplifier inactive. With the selection transistor de-activated, the controller adjusts the potential of the bit line pair to a level corresponding with the intermediate potential. When the selection transistor is activated, the read-out amplifier brings the bit lines to a corresponding low or high potential during an amplification phase, and in a holding phase, it maintains the corresponding bit line potentials. The read-out amplifier includes at least one n-channel field effect transistor. Operation of this circuitry, and of implementations with additional transistors, is further detailed. An independent claim IS INCLUDED FOR the corresponding method of operation.

公开(公告)号：DE59913924D1

公开(公告)日：2006-11-30

申请号：DE59913924

申请日：1999-02-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAVIGNAC DOMINIQUE ,  WIRTH NORBERT ,  WEBER FRANK

IPC: G01R31/26 ,  G01R31/316 ,  G01R31/28

Abstract: The arrangement identifies contact faults on testing integrated circuits with several pins (5) extending from a housing (8) of the integrated circuit. The pins (5) are connected to respective pads (2) on a semiconductor body (1) of the integrated circuit. Pull-up or pull-down devices (9) are provided in the path between the respective pads (2) and the input of the integrated circuit. The pull-up or pull-down devices (9) hold the pads (2) to a high or a low potential by impressing a holding current when, on testing, the respective pin (5) is not contacted, so that an actuation of the circuit part connected to the pin (5) is prevented.

公开(公告)号：DE10124753B4

公开(公告)日：2006-06-08

申请号：DE10124753

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT ,  CHRYSOSTOMIDES ATHANASIA ,  KLING SABINE

IPC: G11C7/06

Abstract: The invention provides a method in which a binary memory cell signal from a; least one memory cell is applied to at least one bit line pair (201t, 201b), the binary memory cell signal from the memory tell is switched through via the bit line pair (201t, 201b) to at least one sense amplifier (202), a binary output signal of the sense amplifier (202) is switched through to a local data line pair (205) as a binary intermediate signal, the binary intermediate signal on the local data line pair (205) is switched through to at least one main data line pair (208) by means of a main data line switching transistor pair (209) in a manner dependent on a row control signal fed via a row control line (210), the main data line switching transistor pair (209) being arranged in the through-plating regions formed between the memory cell arrays.

公开(公告)号：DE102005042269A1

公开(公告)日：2006-04-13

申请号：DE102005042269

申请日：2005-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SICHERT CHRISTIAN ,  WALLNER PAUL

IPC: G11C7/22

Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

公开(公告)号：DE10107666C1

公开(公告)日：2002-08-14

申请号：DE10107666

申请日：2001-02-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AYADI KAMEL ,  MUELLER JOCHEN ,  LINDOLF JUERGEN ,  SAVIGNAC DOMINIQUE ,  DANKOWSKI STEFAN ,  LEHR MATTHIAS UWE ,  BRINTZINGER AXEL ,  FREY ULRICH

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/522

Abstract: The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15') above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15') in order to uncover the surface of the first insulating layer (25); forming a contact (11a') in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15'); and providing an interconnect (40a) for electrical connection of the contact (11a').

公开(公告)号：DE59608801D1

公开(公告)日：2002-04-04

申请号：DE59608801

申请日：1996-07-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEBBEKER HEINZ ,  RECZEK WERNER ,  SAVIGNAC DOMINIQUE ,  TERLETZKI HARTMUD

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02

Abstract: The invention concerns an integrated circuit comprising at least one stray field-effect transistor (Tpar) or a stray diode which contains two adjacent doped regions (2) of the same or opposite types of conduction and an insulating region (1) disposed therebetween. The doped regions (2) are each connected to a connection pad of the integrated circuit. In order to increase resistance to electrostatic discharges, the length (L) of the insulating region (1) in the lateral direction is equal to or greater than the length of the longest discharge path of electrostatic discharge-protective structures (TESD) connected to the connection path (4).

公开(公告)号：DE10045692A1

公开(公告)日：2002-04-04

申请号：DE10045692

申请日：2000-09-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE

IPC: G11C11/401 ,  G11C11/34 ,  G11C11/407 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/404 ,  G11C8/00 ,  G11C5/14

Abstract: An integrated store, has storage cells which each comprise a selection transistor and a storage capacitance with each storage cell, the storage capacitance is connected via the selection transistor to one of several column lines (BLK). With each storage cell, a control terminal of the selection transistor is connected to one of several row-lines (WLN) and with the buffer capacitances in each case one contact (K2) is connected to a further one of the column lines (BLK) and the buffer capacitances (CP) are arranged in such a way that the connections (GB) between the respective buffer capacitance and the contact (K2) is arranged parallel to another one of the row-lines (WLK).