公开(公告)号：DE19843470B4

公开(公告)日：2005-03-10

申请号：DE19843470

申请日：1998-09-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHNEIDER HELMUT ,  SCHAMBERGER FLORIAN

IPC: G11C29/00

公开(公告)号：DE10324448B3

公开(公告)日：2005-02-03

申请号：DE10324448

申请日：2003-05-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENDERS GERHARD ,  VOIGT PETER ,  SCHNEIDER HELMUT

IPC: H01L21/28 ,  H01L21/336

Abstract: A method for fabricating a semiconductor gate structure including depositing at least one sacrificial layer on a semiconductor substrate; patterning the at least one sacrificial layer to form at least one cutout in the at least one sacrificial layer for uncovering the semiconductor substrate; forming a sidewall spacer over the sidewalls of the at least one sacrificial layer in the at least one cutout; forming a gate dielectric on the semiconductor substrate in the cutout; providing a gate electrode in the at least one cutout in the at lest one sacrificial layer; and removing the at least one sacrificial layer for the uncovering the gate electrode surrounded by the sidewall spacer. A semiconductor device is also provided.

公开(公告)号：DE10128254A1

公开(公告)日：2003-03-06

申请号：DE10128254

申请日：2001-06-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUHNE SEBASTIAN ,  FISCHER HELMUT ,  KLEHN BERND ,  BENEDIX ALEXANDER ,  SCHNEIDER HELMUT

IPC: G11C8/14 ,  G11C11/408 ,  G11C5/06

Abstract: An integrated memory has a memory cell array, which is subdivided into a plurality of separate segments. A first and a second local word line in different segments together form a common global word line. The global word line is decoded via a row decoder. The first and second local word lines are connected to a column decoder in such a way that they can be decoded individually and segment by segment in a manner dependent on a column address. The memory thus allows fast and current-saving activation of a word line.

公开(公告)号：DE10102871C2

公开(公告)日：2003-03-06

申请号：DE10102871

申请日：2001-01-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: G11C29/48 ,  G01R31/3187 ,  G11C29/00 ,  H04L7/00

公开(公告)号：DE10138521A1

公开(公告)日：2003-02-27

申请号：DE10138521

申请日：2001-08-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER HELMUT

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/18

Abstract: A circuit part is provided for the generation of control signals and application thereof to the sense amplifiers, made up of generation circuits as in the provided figure. The generation circuits are arranged within the memory cell field adjacent to the sense amplifiers and generate control signals which are directly locally applied to the sense amplifiers, with the exception of a particular number of global control signals. The generation circuits are preferably arranged in the plane of the memory cell fields, in which bands with sense amplifiers and word line drivers overlap.

公开(公告)号：DE59902403D1

公开(公告)日：2002-09-26

申请号：DE59902403

申请日：1999-09-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LE THOAI-THAI ,  LINDOLF DR ,  SCHNEIDER HELMUT

IPC: G11C7/06 ,  G11C7/08 ,  G11C8/08 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4091 ,  H01L27/105 ,  H01L27/108

公开(公告)号：DE59805044D1

公开(公告)日：2002-09-05

申请号：DE59805044

申请日：1998-11-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

IPC: G05F3/24 ,  H03K19/0175

Abstract: A buffer circuit serves for buffering a supply voltage of an integrated circuit. The supply voltage is present between two potential nodes. A series circuit is disposed between the two potential nodes and includes at least two buffer capacitors between which a third potential node is disposed. The third potential node is connected to an additional circuit which influences the potential of the third potential node in such a way that it does not exceed an upper and/or lower limit value when a leakage current occurs through one of the capacitors. The advantage of the buffer circuit is that when there is a defect in just one of the buffer capacitors, the other capacitor is prevented from being destroyed.

公开(公告)号：DE10104701A1

公开(公告)日：2002-08-29

申请号：DE10104701

申请日：2001-02-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT ,  PFEFFERL PETER ,  PFEIFFER JOHANN

IPC: G11C7/18 ,  G11C11/4096 ,  G11C7/14

Abstract: The method involves writing data into the memory simultaneously over the adjacent pairs of data lines. When reading data, data are only read from one of the pairs of data lines. Each data line is connected to a bit line via a switch and the switches to the four data lines are closed before writing data. Independent claims are also included for the following: a memory arrangement with at least two pairs of data lines.

公开(公告)号：DE10021776C2

公开(公告)日：2002-07-18

申请号：DE10021776

申请日：2000-05-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  SCHNEIDER HELMUT ,  SCHOENINGER SABINE ,  MARKERT MICHAEL

IPC: G11C7/06 ,  G11C11/4091

Abstract: At least one of the drive transistors (N1, P1) is arranged with its doping areas between the associated NMOS or PMOS transistors of the read/write amplifiers (N2, N3, P2, P3), and the gate of these drive transistors (N1, P1) is constructed as a two-strip gate (N111, P111).

公开(公告)号：DE59901516D1

公开(公告)日：2002-06-27

申请号：DE59901516

申请日：1999-08-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: G11C29/44 ,  G06F11/20 ,  G11C29/00

Abstract: The memory cells of an integrated memory are successively tested and immediately following the detection of a defect of the memory cell currently being tested, the affected row line or column line is replaced by programming one of the redundant lines. After a certain number of the redundant lines have been programmed, the programming of at least one of the redundant lines is canceled if a further defect is found. This redundant line is programmed for repairing a defect of another memory cell.