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公开(公告)号：KR1020140140151A
公开(公告)日：2014-12-09
申请号：KR1020130060190
申请日：2013-05-28
Applicant: 한국전자통신연구원
CPC classification number: G01S13/103 , G01S7/28 , G01S13/0209 , G01S1/24 , G01S1/42 , G01S7/292 , G01S13/02 , G01S13/56
Abstract: 높은 해상도를 갖는 펄스 레이더 장치를 제시한다. 제시된 장치는 송신 펄스 반복주기를 갖는 송신 트리거 신호를 근거로 펄스를 발생시켜 송신 안테나를 통해 목표물에게로 송신하는 펄스 발생부, 외부로부터의 클록을 이용하여 송신 트리거 신호를 생성하여 펄스 발생부에게로 제공하고 외부로부터의 클록을 이용하여 송신 펄스 반복주기와는 시간차이나는 다수의 클록 신호를 발생시키는 동기화부, 및 외부로부터의 선택신호에 근거하여 다수의 클록 신호에서 어느 한 클록 신호를 선택하여 수신기의 샘플러의 샘플링 클록으로 제공하는 스위치부를 포함한다.
Abstract translation: 提出了一种具有高分辨率的脉冲雷达装置。 所提出的装置包括：脉冲发生单元，其基于具有发送脉冲重复周期的发送触发信号产生脉冲，并通过发送天线将脉冲发送到目标; 通过使用来自外部的时钟产生发送触发信号的同步单元向脉冲发生单元提供发送触发信号，并且使用来自外部的时钟从多个发送脉冲重复周期生成具有时间差的多个时钟信号; 以及切换单元，其基于来自外部的选择信号在时钟信号中选择一个时钟信号，并将时钟信号提供给接收机的采样器作为采样时钟。
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公开(公告)号：KR101449484B1
公开(公告)日：2014-10-13
申请号：KR1020100115078
申请日：2010-11-18
Applicant: 한국전자통신연구원
Abstract: 본 발명은 직접 변환 수신기에 관한 것으로서, 샘플링 주파수에 따라서 입력 전류를 전하 샘플링하는 샘플러부 및 낮은 입력 임피던스를 가지면서 샘플러부의 출력 신호를 수신하여 증폭하고 전류신호를 출력하는 버퍼부를 포함하는 고선형성 믹서 장치와, 믹서 장치의 출력 신호를 데시메이션하고 FIR 필터링 하는 필터 장치를 포함하며, 필터 장치는, 입력 신호를 서로 상이한 샘플링 주기만큼 지연시키고 서로 동일한 또는 상이한 웨이트(weight)를 부여하여 다수의 지연 신호를 생성하여 출력하는 신호전달부와, 신호전달부로부터 출력되는 다수의 지연 신호를 가산하여 결과를 출력하는 가산부를 포함한다.
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公开(公告)号：KR101304596B1
公开(公告)日：2013-09-05
申请号：KR1020090055584
申请日：2009-06-22
Applicant: 한국전자통신연구원
Abstract: CMOS 공정을 이용하여 금속-산화물-금속(MOM) 구조의 평판 캐패시터에 스위치를 적용하여 제어신호에 따라 서로 다른 캐패시턴스를 형성하는 가변 캐패시턴스를 갖는 캐패시터가 개시된다. 상기 가변 캐패시턴스를 갖는 캐패시터는, 하나의 제1 금속층을 포함하는 복수의 금속층 및 상기 복수의 금속층 사이에 개재된 복수의 유전체층을 포함하는 적층구조물; 및 상기 복수의 금속층 중 상기 제1 금속층을 제외한 나머지 금속층 중 적어도 하나의 금속층에 일단이 연결된 적어도 하나의 스위치를 갖는 스위치부를 포함하며, 상기 제1 금속층과 상기 스위치의 타단은 캐패시터의 양 단자가 되며, 상기 스위치의 단락/개방 제어를 통해 상기 양 단자 사이에 적어도 두 개의 캐패시턴스를 제공한다.
가변, 캐패시턴스, 캐패시터, 디지털 제어 발진기, 단위 캐패시턴스, 스위치, CMOS, MOM-
公开(公告)号：KR1020120072261A
公开(公告)日：2012-07-03
申请号：KR1020100134101
申请日：2010-12-23
Applicant: 한국전자통신연구원
CPC classification number: H03L7/0802 , H03L7/085 , H03L2207/50 , H03L7/0991
Abstract: PURPOSE: A fractional digital PLP(Phase-Locked Loop) with an analog phase error compensator is provided to compensate for minute phase error detection and compensation through an analog phase error compensator by mounting the analog phase error compensator on a digital PLP. CONSTITUTION: An arithmetic operation phase error detector(110) comprises a reference accumulator(102), a high speed accumulator(104), a sampler(107), and a subtracter(103). An analog phase error compensator(200) compensates for a minute phase error value of a DCO(Digitally Controlled Oscillator) clock and a reference clock according to the minute phase difference between the reference clock and a re-timed clock. A digital loop gain controller(105) controls loop operation properties. A voltage controlled oscillator(101) changes the frequency of the DCO clock. A re-timed clock generator(106) outputs the re-timed clock by synchronizing the reference clock with the rising edge of the DCO clock.
Abstract translation: 目的：提供具有模拟相位误差补偿器的分数数字PLP（锁相环），通过将模拟相位误差补偿器安装在数字PLP上，通过模拟相位误差补偿器补偿微小相位误差检测和补偿。 构成：算术运算相位误差检测器（110）包括参考累加器（102），高速累加器（104），采样器（107）和减法器（103）。 模拟相位误差补偿器（200）根据参考时钟和定时时钟之间的微小相位差补偿DCO（数字控制振荡器）时钟和参考时钟的微小相位误差值。 数字环路增益控制器（105）控制环路操作属性。 压控振荡器（101）改变DCO时钟的频率。 重新定时的时钟发生器（106）通过使参考时钟与DCO时钟的上升沿同步来输出重新定时的时钟。
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公开(公告)号：KR1020110095132A
公开(公告)日：2011-08-24
申请号：KR1020110003546
申请日：2011-01-13
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A human and animal identifying apparatus capable and a method thereof are provided to selectively stimulate sensation of a detection target and detect reaction of the same, thereby accurately identifying the detection target whether human or animal. CONSTITUTION: A human and animal identifying apparatus includes a detection target sensing part(210), a detection target stimulating part(220), and a detection target identifying part(230). The detection target sensing part is equipped with a detection sensor in a detection area and detects a presence of human and animal. The detection target sensing part includes an stimulation signal generation part(221) and stimulation signal output part(222) and provides the stimulation signal to a detection target(100) in order to selectively stimulate a sense of human and animal. The detection target identification part is comprised of a reaction detecting part(231) and a reaction analyzing part(232). The reaction detecting part detects a reaction of the detection target according to the stimulation signal using an image processing method or distance measurement method. A reaction analyzing part identifies whether the detection target is a human or animal by considering a detection result of the reaction detecting part and kind of a stimulation signal.
Abstract translation: 目的：提供人和动物识别装置及其方法以选择性地刺激检测目标的感觉并检测其检测反应，从而准确地识别检测目标是否人或动物。 构成：人和动物识别装置包括检测对象感测部（210），检测对象刺激部（220）和检测对象识别部（230）。 检测对象检测部在检测区域配备有检测传感器，并检测人和动物的存在。 检测对象感测部包括刺激信号生成部（221）和刺激信号输出部（222），并将刺激信号提供给检测对象（100），以选择性地刺激人与动物的感觉。 检测对象识别部由反应检测部（231）和反应分析部（232）构成。 反应检测部使用图像处理方法或距离测量方法，根据刺激信号检测检测对象的反应。 反应分析部通过考虑反应检测部的检测结果和刺激信号的种类来识别检测对象是人还是动物。
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Patent Agency Ranking
公开(公告)号：KR1020110070675A
公开(公告)日：2011-06-24
申请号：KR1020100027986
申请日：2010-03-29
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A digital RF converter, and a digital RF modulator and a transmitter including the same are provided to effectively increase the dynamic area and SNR of the transmitter without increasing the number of digital RF converting cells. CONSTITUTION: A DSMB(Delta-sigma modulated bits) sub block(331) creates the current of a size corresponding to the lowest n bit of input signals at a first sampling rate. An LSB(Least-Significant Bit) sub block(332) creates the current of a size corresponding to a middle k bit of the input signal at a second sampling rate lower than the first sampling rate. An MSB(Most-Significant Bit) sub block(333) creates the current of a size corresponding to the highest m bit of the input signal at the second sampling rate.
Abstract translation: 目的：提供数字RF转换器，数字RF调制器和包括该数字RF调制器的发射器，以有效增加发射机的动态面积和SNR，而不增加数字RF转换单元的数量。 构成：DSMB（Δ-Σ调制比特）子块（331）以第一采样率产生与最低n位输入信号相对应的大小的电流。 LSB（最低有效位）子块（332）以低于第一采样率的第二采样率产生与输入信号的中间k位相对应的大小的电流。 MSB（最高有效位）子块（333）以第二采样率产生与输入信号的最高m位相对应的大小的电流。
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公开(公告)号：KR100452948B1
公开(公告)日：2004-10-14
申请号：KR1020020081477
申请日：2002-12-18
Applicant: 한국전자통신연구원
IPC: H03K3/027
Abstract: PURPOSE: A flipflop using complementary clocking and a prescaler using the same are provided to improve the current driving capacity by using the complementary relation between an NMOS transistor and a PMOS transistor. CONSTITUTION: A first p-type transistor(mp11) is connected between a supply voltage supply unit and the first node to receive data. A second p-type transistor(mp12) is connected between the first and the second nodes to receive the first clock. A first n-type transistor(mn11) is connected between the second node and the ground to receive the data. A third p-type transistor(mp13) is connected between the supply voltage supply unit and the third node. A second n-type transistor(mn12) is connected between the third and the fourth nodes to receive the first clock. A third n-type transistor(mn13) is connected between the fourth node and the ground. A fourth p-type transistor(mp14) is connected between the supply voltage supply unit and an output terminal. A fourth n-type transistor(mn14) is connected between the output terminal and the ground to receive the second clock. A fifth n-type transistor is connected between the first and the second nodes to receive the second clock. A fifth p-type transistor is connected between the third and the fourth nodes to receive the second clock.
Abstract translation: 目的：提供使用互补时钟的触发器和使用该触发器的预分频器，以通过使用NMOS晶体管和PMOS晶体管之间的互补关系来提高电流驱动能力。 构成：第一P型晶体管（mp11）连接在电源电压供应单元和第一节点之间以接收数据。 第二p型晶体管（mp12）连接在第一和第二节点之间以接收第一时钟。 第一n型晶体管（mn11）连接在第二节点和地之间以接收数据。 第三P型晶体管（mp13）连接在电源电压供应单元和第三节点之间。 第二n型晶体管（mn12）连接在第三和第四节点之间以接收第一时钟。 第三n型晶体管（mn13）连接在第四节点和地之间。 第四P型晶体管（mp14）连接在电源电压提供单元和输出端子之间。 第四n型晶体管（mn14）连接在输出端和地之间以接收第二时钟。 第五n型晶体管连接在第一和第二节点之间以接收第二时钟。 第五p型晶体管连接在第三和第四节点之间以接收第二时钟。
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公开(公告)号：KR100441985B1
公开(公告)日：2004-07-30
申请号：KR1020010070752
申请日：2001-11-14
Applicant: 한국전자통신연구원
IPC: H01P1/15
CPC classification number: H03H7/0115 , H03H2001/0085
Abstract: The present invention relates to an integrated filter circuit for digitally controlling characteristics of inductor and capacitor to thereby produce a controlled resonant frequency. The integrated circuit includes a number of inductors being connected in series between a high frequency input node and a high frequency output node, a plurality of capacitors each connected to a connection node of said each inductors, a plurality of switches, each connected between each capacitor and a ground and a feedback control unit for controlling the switches by sensing an output signal from the high frequency output node to thereby selectively couple each capacitor to the ground through a selected switches based on the sensed output signal.
Abstract translation: 本发明涉及一种用于数字控制电感器和电容器的特性从而产生受控谐振频率的集成滤波器电路。 集成电路包括串联连接在高频输入节点和高频输出节点之间的多个电感器，多个电容器，每个电容器连接到所述每个电感器的连接节点，多个开关，每个开关连接在每个电容器 以及接地和反馈控制单元，用于通过感测来自高频输出节点的输出信号来控制开关，从而基于感测到的输出信号通过选择的开关选择性地将每个电容器耦合到地。
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公开(公告)号：KR100424676B1
公开(公告)日：2004-03-27
申请号：KR1020010047550
申请日：2001-08-07
Applicant: 한국전자통신연구원
IPC: G11C17/00
Abstract: PURPOSE: A low-power ROM is provided to be capable of reducing an area while lowering power consumption at a read operation. CONSTITUTION: Column selection transistors(Ms1-Msn) select one of a plurality of bit lines. A common connection terminal is connected in common to one ends of the column selection transistors, and precharges the bit lines with a charge sharing voltage when the column selection transistors are turned on. A precharge part(Mp1) precharges the common connection terminal with a power supply voltage(VCC). A reference voltage generating part is connected to the precharge part, and generates a reference voltage used to compare voltages of the bit lines. A sense amplifier(SA) receives the reference voltage and a charge sharing voltage of the common connection terminal.
Abstract translation: 目的：提供低功率ROM，以便在读取操作时降低功耗并减小面积。 构成：列选择晶体管（Ms1-Msn）选择多个位线中的一个。 公共连接端子共同连接到列选择晶体管的一端，并且当列选择晶体管导通时利用电荷共享电压预充电位线。 预充电部分（Mp1）利用电源电压（VCC）预充电公共连接端子。 参考电压生成部件连接到预充电部件，并且生成用于比较位线的电压的参考电压。 读出放大器（SA）接收公共连接端子的参考电压和电荷共享电压。
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公开(公告)号：KR100407693B1
公开(公告)日：2003-11-28
申请号：KR1020010039998
申请日：2001-07-05
Applicant: 한국전자통신연구원
IPC: H03B28/00
CPC classification number: G06F1/0356 , G06F1/0328 , G06F2101/04 , G11C17/00
Abstract: The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e., coarse-quantized ROM, coarse-error ROM, fine-quantized ROM and fine-error ROM.
Abstract translation: 本发明涉及一种用于减小直接数字频率合成器（DDFS）中的ROM的尺寸的ROM分割方法，其用于在需要快速频率转换的通信系统中合成频率。 在系统中消耗大部分能量的ROM，提出了一种改进的Nicholas架构来减小ROM的尺寸。 在这种改进的Nicholas架构中，ROM分为粗略ROM和精细ROM，以将相位转换为正弦值。 本发明分别将粗略ROM和精细ROM分成量化ROM和错误ROM。 然后，存储在每个ROM中的值以一定的间隔被分段，并且每个段中的最小量化值被存储在量化ROM中，而原始ROM值和量化ROM值之间的差被存储在错误ROM中。 这样可以减少ROM的大小。 在DDFS中输入的相位值，正弦值是通过加上四个ROM值即粗量化ROM，粗误ROM，精量量ROM和微误差ROM来计算的。
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