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    2.
    发明专利
    未知

    公开(公告)号：DE3886684T2

    公开(公告)日：1994-06-23

    申请号：DE3886684

    申请日：1988-10-13

    Applicant: IBM

    Inventor： HINSBERG WILLIAM DINAN III ,  HOWARD WEBSTER EUGENE ,  WILLSON CARLTON GRANT

    IPC: H01L21/027 ,  H01L21/30 ,  H01L21/336 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/84

    Abstract: A process for making a self-aligned thin film transistor, comprising the steps of: (a) providing a gate which comprises a glass substrate (1), a transparent electrode (2) on top thereof, and a metal electrode (3) on top of said transparent electrode, (b) forming a stack by depositing over said gate a triple layer structure consisting of gate dielectric material (4), active material (5) and a top passivating dielectric (6), (c) coating the top of said triple layer with a dual-tone photoresist (7), (d) exposing said photoresist from the top through a mask having transparent areas, opaque areas and areas transparent to selective wavelengths, using broad band UV light, (e) developing the photoresist by treatment with a solvent, (f) etching the stack with a liquid etchant through to the glass substrate, (g) exposing the photoresist from the bottom through the glass substrate using near UV light, (h) developing the photoresist with a solvent, and (i) etching off the top passivating layer of the stack.

    7.
    发明专利
    未知

    公开(公告)号：DE3886684D1

    公开(公告)日：1994-02-10

    申请号：DE3886684

    申请日：1988-10-13

    Applicant: IBM

    Inventor： HINSBERG WILLIAM DINAN III ,  HOWARD WEBSTER EUGENE ,  WILLSON CARLTON GRANT

    IPC: H01L21/027 ,  H01L21/30 ,  H01L21/336 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/84

    Abstract: A process for making a self-aligned thin film transistor, comprising the steps of: (a) providing a gate which comprises a glass substrate (1), a transparent electrode (2) on top thereof, and a metal electrode (3) on top of said transparent electrode, (b) forming a stack by depositing over said gate a triple layer structure consisting of gate dielectric material (4), active material (5) and a top passivating dielectric (6), (c) coating the top of said triple layer with a dual-tone photoresist (7), (d) exposing said photoresist from the top through a mask having transparent areas, opaque areas and areas transparent to selective wavelengths, using broad band UV light, (e) developing the photoresist by treatment with a solvent, (f) etching the stack with a liquid etchant through to the glass substrate, (g) exposing the photoresist from the bottom through the glass substrate using near UV light, (h) developing the photoresist with a solvent, and (i) etching off the top passivating layer of the stack.

    9.
    发明专利
    未知

    公开(公告)号：DE3667553D1

    公开(公告)日：1990-01-18

    申请号：DE3667553

    申请日：1986-01-24

    Applicant: IBM

    Inventor： HULT ANDERS ,  ITO HIROSHI ,  MACDONALD SCOTT ARTHUR ,  WILLSON CARLTON GRANT

    IPC: H01L21/30 ,  G03F7/20 ,  G03F7/26 ,  G03F7/38 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  G03C1/68 ,  G03F7/10

    Abstract: Negative relief images are generated by a process comprising the use of cationic polymerization and plasma etching. The process comprises a process for generating a negative tone resist image comprising the steps of:(1) coating a substrate with a film that contains a cationic photoinitiator;(2) exposing the film in an imagewise fashion to radiation and thereby generating cationic initiator in the exposed regions of the film;(3) treating the exposed film with a cationic-sensitive monomer to form a film of polymer resistant to plasma etching; and(4) developing the resist image by etching with a plasma.

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