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公开(公告)号:DE102004016705B4
公开(公告)日:2008-04-17
申请号:DE102004016705
申请日:2004-04-05
Applicant: IBM , INFINEON TECHNOLOGIES AG
Inventor: YU CHIENFAN , RUPP THOMAS , DOBUZINSKI DAVID M , DEV PRAKASH C , RENGARAJAN RAJESH , NAEEM MUNIR-UD-DIN , BENEDICT JOHN , FALTERMEIER JOHNATHAN E , MALDEI MICHAEL
IPC: H01L21/283 , H01L21/311 , H01L21/60 , H01L21/8239 , H01L21/8242 , H01L23/485 , H01L29/768
Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.
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公开(公告)号:DE102006030869A1
公开(公告)日:2008-01-10
申请号:DE102006030869
申请日:2006-07-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor: FATHULLA AHMAD , LACKNER GERALD , RUPP THOMAS , SANTOS RODRIGUEZ FRANCISCO JAV , SCHOENHERR HELMUT , SCHULZE HANS-JOACHIM
IPC: H01L21/306 , C30B25/02
Abstract: The production of a semiconductor wafer useful in e.g. chip cards, comprises providing a semiconductor substrate (1) from a first semiconductor material with a first surface and a second surface, which faces the first surface, applying a first semiconductor layer (2) from a second semiconductor material epitaxially on the second surface, and partially removing the substrate from the first semiconductor layer. The epitaxial application of a second semiconductor layer (3) from a third semiconductor material on the first semiconductor layer takes place to the desired target thickness. The production of a semiconductor wafer useful in e.g. chip cards, comprises providing a semiconductor substrate (1) from a first semiconductor material with a first surface and a second surface, which faces the first surface, applying a first semiconductor layer (2) from a second semiconductor material epitaxially on the second surface, and partially removing the substrate from the first semiconductor layer. The epitaxial application of a second semiconductor layer (3) from a third semiconductor material on the first semiconductor layer takes place to the desired target thickness. After the partial removing, the first semiconductor layer is partly removed via corroding. Before corroding a prefabricated device is attached as an etching mask at the first surface of the substrate. The device covers an external area of the first surface and limits an opening that releases an internal area of the first surface of the substrate, and is again removed after corroding. A semiconductor component (4) is formed in the first- and second semiconductor layer before the partial removing of the substrate.
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公开(公告)号:DE102004016705A1
公开(公告)日:2004-11-25
申请号:DE102004016705
申请日:2004-04-05
Applicant: IBM , INFINEON TECHNOLOGIES AG
Inventor: YU CHIENFAN , RUPP THOMAS , DOBUZINSKI DAVID M , DEV PRAKASH C , RENGARAJAN RAJESH , NAEEM MUNIR-UD-DIN , BENEDICT JOHN , FALTERMEIER JOHNATHAN E , MALDEI MICHAEL
IPC: H01L21/311 , H01L21/60 , H01L21/8242 , H01L23/485 , H01L21/283
Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.
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公开(公告)号:DE102021118992A1
公开(公告)日:2022-02-24
申请号:DE102021118992
申请日:2021-07-22
Applicant: INFINEON TECHNOLOGIES AG
Inventor: NAPETSCHNIG EVELYN , ERBERT CHRISTOFFER , RUPP THOMAS , SCHÄFFER CARSTEN , HIRSCHLER JOACHIM , BRANDENBURG JENS , ZISCHANG JULIA , HUMBEL OLIVER
Abstract: Vorgeschlagen wird eine Halbleitervorrichtung (100). Die Halbleitervorrichtung (100) enthält eine Verdrahtungs-Metallschichtstruktur (102). Die Halbleitervorrichtung (100) enthält ferner eine direkt auf der Verdrahtungs-Metallschichtstruktur (102) angeordnete Dielektrikumsschichtstruktur (104). Die Halbleitervorrichtung (100) enthält überdies eine zumindest teilweise direkt auf der Dielektrikumsschichtstruktur (104) angeordnete Bondingpad-Metallschichtstruktur (106). Eine Schichtdicke (td) der Dielektrikumsschichtstruktur (104) reicht von 1% bis 30% einer Schichtdicke (tw) der Verdrahtungs-Metallschichtstruktur (102). Die Verdrahtungs-Metallschichtstruktur (102) und die Bondingpad-Metallschichtstruktur (106) sind durch Öffnungen (108) in der Dielektrikumsschichtstruktur (104) elektrisch verbunden.
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公开(公告)号:DE102004013932A1
公开(公告)日:2005-10-27
申请号:DE102004013932
申请日:2004-03-22
Applicant: INFINEON TECHNOLOGIES AG
Inventor: GUTT THOMAS , LASKA THOMAS , RUPP THOMAS , SCHAEFFER CARSTEN , SCHMIDT GERHARD , SCHULZE HOLGER
IPC: H01L21/22 , H01L21/268 , H01L21/324 , H01L21/329 , H01L21/331 , H01L21/336
Abstract: A first main surface/front side (9) has a metal coating (5). A second main surface/rear side (10) has first (3) and second (4) areas doped with a power-type doping agent. Doped areas on a semiconductor substrate's rear (1) side are treated at a temperature above a melting temperature for the metal coating on the front side. An independent claim is also included for a method for producing semiconductor components with a vertical structure so as to handle heat in a semiconductor substrate.
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公开(公告)号:DE102004011175A1
公开(公告)日:2005-09-29
申请号:DE102004011175
申请日:2004-03-08
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SCHULZE HANS-JOACHIM , HILLE FRANK , RUPP THOMAS
IPC: H01L21/265 , H01L21/322 , H01L21/331
Abstract: The method involves placing a doping material with certain dosage in an area near an outer surface of a semiconductor. The semiconductor is subjected to a specified temperature during curing treatment, where the temperature should not exceed 550 degree Celsius. The material and its dosage are selected and introduced into the semiconductor in such a way that the material makes the semiconductor amorphous in the area.
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