公开(公告)号：US20240260168A1

公开(公告)日：2024-08-01

申请号：US18565359

申请日：2022-06-08

Applicant: VITESCO TECHNOLOGIES GMBH

Inventor： Detlev Bagung ,  Christina QUEST-MATT ,  Holger BALDREICH

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K1/0206 ,  H05K3/0094 ,  H05K3/341 ,  H05K2201/09545 ,  H05K2201/09572 ,  H05K2201/09609

Abstract: A circuit board (1) for a power semiconductor module (13), having at least one top side (2) and one bottom side (3), wherein at least one mounting area (4) for a power semiconductor component (12) is provided on the top side (2), wherein on the mounting area (4), at least one solder layer (8) is provided for connecting at least one power semiconductor component (12) to the mounting area (4), which layer is divided into regions (9) that are separated from one another by means of intermediate spaces (11), and wherein multiple thermal vias (5) are provided in the circuit board (1) and extend from the top side (2) to the bottom side (3) of the circuit board (2) in the region of the mounting area (4), wherein each upper opening (6) of the thermal vias (5) is directly surrounded by a respective region (9) of the solder layer (8) and each lower opening (7) of the vias (5) is covered by a layer (10) of electrically insulating material.

公开(公告)号：US11864316B2

公开(公告)日：2024-01-02

申请号：US17630630

申请日：2021-07-16

Applicant: Fujikura Ltd.

Inventor： Naoki Oyaizu ,  Yusuke Fujita ,  Toshiaki Inoue ,  Shinya Kashima

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H05K2201/0305 ,  H05K2201/09481 ,  H05K2201/09545 ,  H05K2201/09563

Abstract: A wiring substrate includes a first insulating layer, a first conductor layer, and a plurality of filled vias. The first insulating layer has a first surface and a second surface positioned on a side opposite to the first surface. The first conductor layer is formed on the first surface of the first insulating layer. The plurality of filled vias are formed inside the first insulating layer. The plurality of filled vias each have a structure in which a via hole penetrating the first insulating layer is filled with a metal. The first conductor layer includes a pad. The pad overlaps the plurality of filled vias in a plan view from a thickness direction of the first insulating layer and is connected to the plurality of filled vias.

公开(公告)号：US20230319978A1

公开(公告)日：2023-10-05

申请号：US17713347

申请日：2022-04-05

Applicant: Dell Products L.P.

Inventor： William Andrew Smith ,  Mallikarjun Vasa ,  Bhyrav M. Mutnury

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K1/0218 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09518 ,  H05K2201/09545

Abstract: An information handling system includes a printed circuit board, a surface mount connector including first and second surface mount connector portions, first and second different pairs, and a ground plane. The first and second surface mount connector portions are mounted on the printed circuit board. The first differential pair is located on the first surface mount connector portion, and the second differential pair is located on the second surface mount connector portion. The ground plane is located in between the first and second surface mount connector portions within the printed circuit board. The first ground via is in physical communication with the ground plane and a first ground pad on a surface of the printed circuit board. The second ground via is in physical communication with the ground plane and a second ground pad on the surface of the printed circuit board.

公开(公告)号：US11683886B2

公开(公告)日：2023-06-20

申请号：US17568120

申请日：2022-01-04

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Toshiki Shirotori

IPC: H05K1/11 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0959 ,  H05K2201/09545 ,  H05K2201/09563

Abstract: A wiring substrate includes: a base material; a first through-hole and a second through-hole that are formed in the base material; magnetic material that is filled in the first through-hole; a third through-hole that is formed in the magnetic material; a first plating film that covers an inner wall surface of the third through-hole; and a second plating film that covers an inner wall surface of the second through-hole and the first plating film. The first plating film includes a first electroless plating film that is in contact with the inner wall surface of the third through-hole, and a first electrolytic plating film that is laminated on the first electroless plating film.

公开(公告)号：US20230180397A1

公开(公告)日：2023-06-08

申请号：US17542867

申请日：2021-12-06

Applicant: R&D Circuits

Inventor： Donald Eric Thompson

IPC: H05K3/42 ,  H05K3/00 ,  H05K3/36 ,  H05K1/18 ,  H05K1/02 ,  C25D7/00 ,  C25D3/38 ,  C25D5/02

CPC classification number: H05K3/426 ,  H05K3/0047 ,  H05K3/368 ,  H05K1/182 ,  H05K1/0222 ,  C25D7/00 ,  C25D3/38 ,  C25D5/02 ,  H05K2201/10325 ,  H05K2201/09072 ,  H05K2201/09545 ,  H05K2203/0723 ,  H05K2201/10409 ,  H05K2201/10303

Abstract: The present invention provides a novel method of constructing a coax spring-pin socket that furnishes better performance and is easier to manufacture in volume using common dielectrics and copper plating. This is accomplished by, in application, a lamination of PCB dielectric layers. This dielectric block is then drilled, plated, etched, and drilled in steps for the construction of a coaxial structure for the signal pins, and a ground structure for ground pins. This design process that can be quickly adjusted and customized for each design.

公开(公告)号：US20180110149A1

公开(公告)日：2018-04-19

申请号：US15559975

申请日：2016-03-23

Applicant: SAFRAN ELECTRONICS & DEFENSE

Inventor： Francois GUILLOT ,  Pascal SPOOR ,  Patrice CHETANNEAU

IPC: H05K7/14 ,  G06F1/18 ,  H05K1/11 ,  H05K3/46 ,  H05K3/00 ,  H05K3/42 ,  H01R12/70 ,  H01R12/71

CPC classification number: H05K7/1439 ,  G06F1/184 ,  H01R12/7064 ,  H01R12/716 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0011 ,  H05K3/0094 ,  H05K3/421 ,  H05K3/4644 ,  H05K7/1412 ,  H05K7/1445 ,  H05K7/1452 ,  H05K7/1459 ,  H05K2201/0104 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/10189 ,  H05K2201/10295

Abstract: The present invention concerns a backplane electronic board (20) having on inner face (142) suitable for bein g connected to electronic board connectors (12) and an outer face (143) suitable for being connected lo an outer connector (15), the backplane board (20) being characterised in that it has blind holes opening on ihe inner face (142) of some, and holes opening on the outer face (143) of same, the holes being suitable for receiving press-fit connection elements and forming therewith an electrical connection point.

公开(公告)号：US09872393B2

公开(公告)日：2018-01-16

申请号：US14886581

申请日：2015-10-19

Applicant: Avary Holding (Shenzhen) Co., Limited ,  HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd. ,  GARUDA TECHNOLOGY CO., LTD.

Inventor： Tzu-Chien Yeh

IPC: H01K3/10 ,  H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K1/09 ,  H05K1/03 ,  H05K3/18 ,  H05K3/46 ,  H05K3/40

CPC classification number: H05K1/184 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/092 ,  H05K1/111 ,  H05K1/115 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/0203 ,  H05K2201/0391 ,  H05K2201/09545 ,  H05K2203/0278 ,  H05K2203/122 ,  H05K2203/1536 ,  Y10T29/49165

Abstract: A circuit board includes a core layer, at least one passive component, a first and a second conductive wire layers, at least one contact pad, and a resin packing layer. The core layer defines at least one through hole to receive the passive component. The first and the second conductive wire layers are connected to two opposite surfaces of the core layer. Each contact pad is positioned between and connected to one passive component and the first conductive wire layer. The resin packing layer is filled among the core layer, each passive component, each contact pad, the first and the second conductive wire layers. The resin packing layer can connect the first and the second conductive wire layers to the core layer, and connect the core layer, each passive component, and each contact pads to each other.

公开(公告)号：US09867290B2

公开(公告)日：2018-01-09

申请号：US14834205

申请日：2015-08-24

Applicant: Multek Technologies Ltd.

Inventor： Kwan Pen ,  Pui Yin Yu

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H05K3/00 ,  H05K3/06 ,  H05K3/18

CPC classification number: H05K1/115 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0058 ,  H05K3/06 ,  H05K3/181 ,  H05K3/188 ,  H05K3/42 ,  H05K3/422 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/095 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/10303

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

公开(公告)号：US09775231B2

公开(公告)日：2017-09-26

申请号：US14947091

申请日：2015-11-20

Applicant: Amphenol Corporation

Inventor： Marc B. Cartier, Jr.

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/40 ,  H05K1/11 ,  H01R43/20

CPC classification number: H05K1/0222 ,  H01R43/205 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/025 ,  H05K1/0251 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/07 ,  H05K2201/09063 ,  H05K2201/09318 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/097 ,  H05K2201/09718 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/10189

Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns comprising: dual diameter first and second signal vias forming a differential signal pair, the first and second signal vias being configured to accept contact tails of signal conductors of a connector; dual diameter ground shadow vias adjacent to each of the first and second signal vias, wherein the dual diameter shadow ground vias have a reversed diameter configuration with respect to the dual diameter first and second signal vias; and ground vias configured to accept contact tails of ground conductors of the connector.

公开(公告)号：US09761972B2

公开(公告)日：2017-09-12

申请号：US15200695

申请日：2016-07-01

Applicant: MERCURY SYSTEMS, INC.

Inventor： Philip Beucler ,  Daniel Coolidge ,  Darryl J. McKenney ,  Kevin Jorczak

IPC: H01R9/05 ,  H01R12/71 ,  H01R12/58 ,  H01R13/652 ,  H05K1/18 ,  H05K3/34 ,  H05K1/02 ,  H05K1/11

CPC classification number: H01R12/716 ,  H01R4/028 ,  H01R9/091 ,  H01R12/526 ,  H01R12/58 ,  H01R12/714 ,  H01R13/05 ,  H01R13/405 ,  H01R13/652 ,  H05K1/0213 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/184 ,  H05K3/308 ,  H05K3/34 ,  H05K3/421 ,  H05K2201/09545 ,  H05K2201/09827 ,  H05K2201/10098 ,  H05K2201/10189 ,  H05K2201/10295 ,  H05K2201/1078 ,  H05K2201/10803 ,  H05K2201/10878 ,  H05K2201/10901 ,  Y02P70/611

Abstract: An RF connector includes a conductive pin for carrying an RF signal. The conductive pin has a first longitudinal end that serves to interface with a male RF connector to receive the RF signal. The pin also includes a second longitudinal end for connecting with a printed circuit board (PCB). The second longitudinal end may be tapered, and the pin may have a groove formed above the tapered end. A housing encircles the conductive pin. The housing is shaped and sized to accept the male RF connector. A grounding element may be positioned on the bottom of the housing. The grounding element is to contact the PCB when the connector is connected to the PCB. The grounding element may be ring-shaped and soldered to the housing or epoxied to the housing.