公开(公告)号：US20170118844A1

公开(公告)日：2017-04-27

申请号：US15175378

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce J. CHAMBERLIN ,  Andreas HUBER ,  Harald HUELS ,  Thomas STRACH ,  Thomas-Michael WINKEL

IPC: H05K3/34 ,  H05K3/40 ,  B23K1/00 ,  H05K3/00 ,  B23K1/20 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K1/184 ,  B23K1/0016 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/111 ,  H05K1/113 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/185 ,  H05K1/186 ,  H05K3/0047 ,  H05K3/3447 ,  H05K3/429 ,  H05K3/46 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09345 ,  H05K2201/09381 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/1006 ,  H05K2201/10174

Abstract: Embedding a discrete electrical device in a printed circuit board (PCB) includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to an electrically conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first electrical device contact device and the electrically conductive structure in the first layer; and establishing a second electrical connection between a second electrical device contact and a second layer, the second layer being one of the electrically conductive layers of a second horizontal core section.

公开(公告)号：US20170062020A1

公开(公告)日：2017-03-02

申请号：US15351580

申请日：2016-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi BETSUI ,  Naoto TAOKA ,  Motoo SUWA ,  Shigezumi MATSUI ,  Norihiko SUGITA ,  Yoshiharu FUKUSHIMA

IPC: G11C5/04 ,  G11C5/06 ,  H01L25/18 ,  H01L23/00 ,  H05K1/18 ,  H01L23/498

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

公开(公告)号：US20160345427A1

公开(公告)日：2016-11-24

申请号：US15228519

申请日：2016-08-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yu ISHIWATA ,  Takahiro AZUMA

IPC: H05K1/02 ,  H05K9/00 ,  H03H7/00 ,  H01L23/552

CPC classification number: H05K1/0216 ,  H01L23/552 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15313 ,  H01L2924/19106 ,  H01Q1/48 ,  H01Q1/526 ,  H03H7/004 ,  H05K1/0233 ,  H05K9/0075 ,  H05K2201/093

Abstract: A noise reducing electronic component is used as mounted on a circuit board. The noise reducing electronic component includes: a floating electrode disposed so as to be capacitively coupled to a ground conductor of the circuit board; a radiation element connected to the floating electrode; and a shielding member to shield electromagnetic waves radiated from the radiation element. With this noise reducing electronic component, noise in a printed circuit board and the like can be reduced.

Abstract translation: 降噪电子部件被安装在电路板上。 降噪电子部件包括：浮置电极，其设置成电容耦合到电路板的接地导体; 连接到浮动电极的辐射元件; 以及屏蔽构件，用于屏蔽从辐射元件辐射的电磁波。 通过这种减少噪声的电子部件，可以降低印刷电路板中的噪声等。

公开(公告)号：US20160334279A1

公开(公告)日：2016-11-17

申请号：US14714005

申请日：2015-05-15

Applicant: Google Inc.

Inventor： Adam Mittleman ,  Ian Charles Smith ,  Daniel Adam Warren ,  William Raeming Dong ,  Jeff Wheeler

IPC: G01J5/06 ,  G01J5/00 ,  G01J5/10 ,  H05K1/02

CPC classification number: G01J5/06 ,  G01J5/0014 ,  G01J5/0205 ,  G01J5/04 ,  G01J5/10 ,  G08B13/189 ,  G08B13/191 ,  H05K1/0201 ,  H05K1/0298 ,  H05K2201/09063 ,  H05K2201/093 ,  H05K2201/09363 ,  H05K2201/0969 ,  H05K2201/10106 ,  H05K2201/10151 ,  H05K2201/10522 ,  H05K2201/10575 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A multilayered circuit board having a metal-free region vertically extending through at least a portion of a conductive layer, which lies generally parallel to a horizontal plane, vertically spaced from an outer surface. Heat-emitting and heat-sensitive components are mounted on the outer surface. The heat-emitting component is vertically and laterally spaced from the metal-free region, whereas the heat-sensitive component is vertically spaced and laterally aligned within the metal-free region such that the metal-free region is a thermal barrier that shields heat-sensitive component from radial heat flowing from the heat-emitting component.

Abstract translation: 一种多层电路板，其具有垂直延伸穿过导电层的至少一部分的无金属区域，该导电层大致平行于与外表面垂直间隔的水平平面。 发热和热敏元件安装在外表面上。 发热部件与无金属区域垂直和横向间隔开，而热敏部件在无金属区域内垂直间隔开并横向对准，使得无金属区域是屏蔽热 - 来自发热部件的径向热的敏感部件。

公开(公告)号：US09462709B2

公开(公告)日：2016-10-04

申请号：US14407557

申请日：2013-09-26

Applicant: KYOCERA Corporation

Inventor： Yoshiki Kawazu

IPC: H01L23/055 ,  H05K1/18 ,  H05K5/02 ,  H05K5/00 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K5/0091 ,  H01L23/055 ,  H01L2924/0002 ,  H05K1/0225 ,  H05K1/115 ,  H05K1/116 ,  H05K1/181 ,  H05K5/0239 ,  H05K5/0247 ,  H05K2201/093 ,  H05K2201/09627 ,  H05K2201/09718 ,  H05K2201/2018 ,  H01L2924/00

Abstract: An element housing package includes a substrate, a frame body, and an input-output terminal. The input-output terminal has a wiring conductor formed in a stacked body consisting of dielectric layers and ground layers which are alternately laminated, to extend through an inside of the stacked body, and a lead terminal connected to the wiring conductor. A non-formation region is provided in the ground layers around the wiring conductor, which passes through the inside of the input-output terminal in a vertical direction of the stacked body. The non-formation region has, in order from an upper side toward a lower side, a first non-formation section, a second non-formation section having an area smaller than that of the first non-formation section, and a third non-formation section having an area larger than that of the second non-formation section.

Abstract translation: 元件外壳包装件包括基板，框体和输入 - 输出端子。 输入输出端子具有形成在层叠体中的布线导体，该堆叠体由交替层叠的电介质层和接地层构成，以延伸穿过层叠体的内部，以及引线端子与布线导体连接。 在布线导体周围的接地层中设置非形成区域，该布线导体在层叠体的垂直方向上穿过输入输出端子的内部。 非形成区域具有从上侧朝向下侧的顺序，具有第一非形成部，具有比第一非成形部的面积小的面积的第二非成形部， 形成部具有比第二非成形部的面积大的面积。

公开(公告)号：US09445492B2

公开(公告)日：2016-09-13

申请号：US13351108

申请日：2012-01-16

Applicant: Nan-Jang Chen ,  Hong-Chin Lin

Inventor： Nan-Jang Chen ,  Hong-Chin Lin

IPC: H05K1/16 ,  H05K1/02 ,  H05K3/22

CPC classification number: H05K1/0216 ,  H01L2924/0002 ,  H05K3/222 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/10363 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A printed circuit board is disclosed. The printed circuit board comprises a substrate having a top surface and a bottom surface. A ground plane is on the bottom surface. A signal trace is on the top surface along a first direction. At least two isolated power planes are on the top surface adjacent to opposite sides of the signal trace, respectively. A conductive connection along a second direction couples to the two power planes, across the signal trace without electrically connecting to the signal trace, wherein the signal trace doesn't pass over any split of the ground plane.

Abstract translation: 公开了印刷电路板。 印刷电路板包括具有顶表面和底表面的基底。 地平面位于底面。 信号迹线沿着第一方向在顶表面上。 至少两个隔离的电源平面分别位于与信号迹线的相对侧相邻的顶表面上。 沿着第二方向的导电连接跨过信号迹线耦合到两个电源层，而不与电信号迹线电连接，其中信号迹线不经过接地平面的任何分裂。

公开(公告)号：US09414496B2

公开(公告)日：2016-08-09

申请号：US14575223

申请日：2014-12-18

Applicant: Oracle International Corporation

Inventor： Ricki Dee Williams ,  Ray Ping-kwan Chan

IPC: H01L23/48 ,  H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/32 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/0251 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0298 ,  H05K2201/093 ,  H05K2201/10015 ,  H05K2201/10545

Abstract: Implementations of the present disclosure involve an apparatus and/or method for a large array of AC coupling/DC blocking capacitors on a printed circuit board (PCB) of a microelectronic circuit. The method provides for the placement of the blocking capacitors (and associated vias) to be placed on/through the PCB in a small area while yielding low crosstalk or interference between the vias. In one particular embodiment, the blocking capacitors are placed on the PCB in an alternating pattern, with a pair of blocking capacitors placed on the top side of the PCB followed by a pair of blocking capacitors on the bottom side of the PCB, and so on. Further, top side capacitor vias may be back-drilled from the bottom side and bottom side capacitor vias may be back-drilled from the top side.

Abstract translation: 本公开的实施方案涉及用于微电子电路的印刷电路板（PCB）上的大量AC耦合/隔直电容器阵列的装置和/或方法。 该方法提供了在小面积内放置在PCB上/通过PCB的隔离电容器（和相关通孔）的放置，同时在通孔之间产生低串扰或干扰。 在一个特定实施例中，隔离电容器以交替模式放置在PCB上，一对隔离电容器放置在PCB的顶侧，之后是PCB底部的一对阻塞电容器，等等 。 此外，顶侧电容器通孔可以从底侧回钻，并且底侧电容器通孔可以从顶侧反向钻出。

公开(公告)号：US20150237714A1

公开(公告)日：2015-08-20

申请号：US14185505

申请日：2014-02-20

Applicant: QUALCOMM Incorporated

Inventor： Ryan Michael Coutts ,  Yuancheng Christopher Pan

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/30 ,  H05K1/18 ,  H05K1/09

CPC classification number: H05K1/0231 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4697 ,  H05K2201/093 ,  H05K2201/10015 ,  H01L2924/014

Abstract: A package substrate is provided that includes a substrate and a capacitor. The substrate comprises a cavity penetrating a core layer and metal layers of the substrate. The capacitor comprises electrode pads and is disposed in the cavity. One of the metal layers of the substrate includes a discontinuous metal plane, and the electrode pads directly contact the discontinuous metal plane.

Abstract translation: 提供了包括基板和电容器的封装基板。 衬底包括穿透芯层的空腔和衬底的金属层。 电容器包括电极焊盘并且设置在空腔中。 衬底的金属层之一包括不连续的金属平面，并且电极焊盘直接接触不连续的金属平面。

公开(公告)号：US20150173214A1

公开(公告)日：2015-06-18

申请号：US14407557

申请日：2013-09-26

Applicant: KYOCERA Corporation

Inventor： Yoshiki Kawazu

IPC: H05K5/00 ,  H05K1/18 ,  H05K5/02 ,  H01L23/055

CPC classification number: H05K5/0091 ,  H01L23/055 ,  H01L2924/0002 ,  H05K1/0225 ,  H05K1/115 ,  H05K1/116 ,  H05K1/181 ,  H05K5/0239 ,  H05K5/0247 ,  H05K2201/093 ,  H05K2201/09627 ,  H05K2201/09718 ,  H05K2201/2018 ,  H01L2924/00

Abstract: An element housing package includes a substrate, a frame body, and an input-output terminal. The input-output terminal has a wiring conductor formed in a stacked body consisting of dielectric layers and ground layers which are alternately laminated, to extend through an inside of the stacked body, and a lead terminal connected to the wiring conductor. A non-formation region is provided in the ground layers around the wiring conductor, which passes through the inside of the input-output terminal in a vertical direction of the stacked body. The non-formation region has, in order from an upper side toward a lower side, a first non-formation section, a second non-formation section having an area smaller than that of the first non-formation section, and a third non-formation section having an area larger than that of the second non-formation section.

Abstract translation: 元件外壳包装件包括基板，框体和输入 - 输出端子。 输入输出端子具有形成在层叠体中的布线导体，该堆叠体由交替层叠的电介质层和接地层构成，以延伸穿过层叠体的内部，以及引线端子与布线导体连接。 在布线导体周围的接地层中设置非形成区域，该布线导体在层叠体的垂直方向上穿过输入输出端子的内部。 非形成区域具有从上侧朝向下侧的顺序，具有第一非形成部，具有比第一非成形部的面积小的面积的第二非成形部， 形成部具有比第二非成形部的面积大的面积。

公开(公告)号：US20140312851A1

公开(公告)日：2014-10-23

申请号：US14255323

申请日：2014-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyun BYUN

IPC: H02J7/00 ,  H02H9/04

CPC classification number: H02H9/04 ,  H05K1/0257 ,  H05K1/167 ,  H05K1/181 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09727 ,  H05K2201/10022

Abstract: An apparatus for preventing an electric overstress in an electronic device, which is capable of protecting the electronic device from the electric overstress is provided. The apparatus includes an interface unit for connecting the electronic device to an external device, includes an electric power terminal which is included in the interface unit and includes a first electric power terminal and a second electric power terminal which are electrically separated, and an electric overstress preventing unit connected with the first and second electric power terminals.

Abstract translation: 提供了一种用于防止电子装置中的电力过载的装置，其能够保护电子装置免受电力过载。 该装置包括用于将电子设备连接到外部设备的接口单元，包括接口单元中包括的电力端子，并且包括电气分离的第一电力端子和第二电力端子，以及电力过载 与第一和第二电力端子连接的防止单元。