公开(公告)号：US20240090134A1

公开(公告)日：2024-03-14

申请号：US18515892

申请日：2023-11-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshihito OTSUBO ,  Hirofumi OIE

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H05K2201/0212 ,  H05K2201/0707 ,  H05K2201/09472 ,  H05K2201/095 ,  H05K2201/1006 ,  H05K2201/10098 ,  H05K2201/10287

Abstract: An electronic circuit module includes: a substrate; a first electronic component mounted on one main surface of the substrate; a substrate electrode provided on the one main surface; a second electronic component supported on a support surface opposite to a surface facing the one main surface of the first electronic component; a conductor provided on the support surface of the first electronic component; a wire connected to the conductor and the substrate electrode; and a component electrode provided on a surface of the second electronic component and electrically connected to the conductor.

公开(公告)号：US20190191565A1

公开(公告)日：2019-06-20

申请号：US16283858

申请日：2019-02-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takahiro Oka ,  Yuki Takemori ,  Kazuo Kishida ,  Hiromichi Kawakami ,  Yukio Yamamoto ,  Kensuke Otake

IPC: H05K1/18 ,  H01L23/13 ,  H01L23/15 ,  H01L23/498 ,  H05K1/11 ,  H05K1/03 ,  H05K3/34

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4864 ,  H01L21/4867 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13017 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/014 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/18 ,  H05K3/1216 ,  H05K3/26 ,  H05K3/34 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4061 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/10795 ,  H05K2201/1081

Abstract: An electronic device that includes an electronic component mounted on a multilayer ceramic substrate. The electronic component includes a connection terminal on the mounting surface side thereof, the connection terminal having an end with a rounded convex shape when viewed in cross section. The multilayer ceramic substrate includes a recessed portion at a position corresponding to the connection terminal, the recessed portion having a rounded concave shape when viewed in cross section, and a surface electrode disposed on at least part of the recessed portion and electrically connected to the connection terminal.

公开(公告)号：US09966333B2

公开(公告)日：2018-05-08

申请号：US15725144

申请日：2017-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H05K1/11 ,  H05K1/16 ,  H05K1/09 ,  H05K1/03 ,  H05K7/00 ,  H05K1/18 ,  H01L23/498 ,  H05K1/02 ,  H01L21/48 ,  H05K3/00 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; (3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and (4) a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace, wherein the first dielectric structure defines at least one opening, and a periphery of the opening corresponds to a periphery of the through hole of the second dielectric structure.

公开(公告)号：US20170149155A1

公开(公告)日：2017-05-25

申请号：US14952242

申请日：2015-11-25

Applicant: MERCURY SYSTEMS, INC.

Inventor： Darryl J. MCKENNEY ,  Absu METHRATTA ,  Erica OUELLETTE

IPC: H01R12/71 ,  H05K1/02 ,  H01R12/58

CPC classification number: H01R12/58 ,  H01R4/028 ,  H01R12/00 ,  H01R12/526 ,  H01R12/714 ,  H01R12/716 ,  H01R13/05 ,  H01R13/405 ,  H01R13/652 ,  H05K1/0213 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/111 ,  H05K1/112 ,  H05K1/115 ,  H05K1/181 ,  H05K1/184 ,  H05K3/308 ,  H05K3/34 ,  H05K3/3421 ,  H05K3/42 ,  H05K3/421 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09827 ,  H05K2201/10098 ,  H05K2201/10189 ,  H05K2201/10295 ,  H05K2201/1078 ,  H05K2201/10803 ,  H05K2201/10871 ,  H05K2201/10878 ,  H05K2201/10901 ,  H05K2203/0455 ,  Y02P70/611

Abstract: According to exemplary embodiments, a tapered surface interconnect is formed on a printed circuit board (PCB). A compliant pin of an electrical connector may be coupled to the tapered surface interconnect and soldered thereto. The surface interconnect may be formed by drilling through one or more layers of the PCB. The depth of the surface interconnect may be shorter than a height or a thickness of the PCB. The surface interconnect may have a tapered side wall to allow for a better fit with a tapered compliant pin. The inclination of the side wall of the surface interconnect may be linear or concave. The intersection between the tapered sidewall and the bottom of the surface interconnect may be rounded to minimize pin insertion issues and may allow for easier solder flux evacuation from the surface interconnect during the soldering process. The compliant pin may be soldered into place upon being coupled to the tapered surface interconnect.

公开(公告)号：US20170148723A1

公开(公告)日：2017-05-25

申请号：US15340945

申请日：2016-11-01

Applicant: Intel Corporation

Inventor： Ravindra V. Tanikella

IPC: H01L23/498 ,  H01L23/31 ,  C08K9/10 ,  C08G73/12 ,  C08K3/36 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49894 ,  C08F283/04 ,  C08G73/121 ,  C08K3/36 ,  C08K9/10 ,  C08K2201/011 ,  C08L79/08 ,  C08L2666/66 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/1163 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

公开(公告)号：US20170077023A1

公开(公告)日：2017-03-16

申请号：US15364143

申请日：2016-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

Abstract translation: 半导体衬底包括：1）具有第一表面和与第一表面相对的第二表面的第一电介质结构; 2）具有与第三表面相对的第三表面和第四表面的第二介电结构，其中第四表面面向第一表面，第二介电结构限定从第三表面延伸到第四表面的通孔，其中腔是 由通孔和第一电介质结构限定; 3）设置在第一介电结构的第一表面上的第一图案化导电层; 以及4）第二图案化导电层，设置在所述第一介电结构的第二表面上并且包括至少一个导电迹线。 第一介电结构限定至少一个开口以暴露第二图案化导电层的一部分。

公开(公告)号：US20170042026A1

公开(公告)日：2017-02-09

申请号：US14820572

申请日：2015-08-07

Applicant: Unimicron Technology Corp.

Inventor： Kuan-Hsi Wu ,  Pi-Te Pan ,  Chang-Fu Chen

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  H05K1/02 ,  H05K3/10

CPC classification number: H05K1/119 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/113 ,  H05K1/116 ,  H05K3/0023 ,  H05K3/0097 ,  H05K3/10 ,  H05K3/303 ,  H05K3/3452 ,  H05K3/4007 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0367 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2203/0562 ,  H05K2203/1536 ,  Y02P70/611

Abstract: A circuit board including a substrate, a photo imageable dielectric layer and a plurality of conductive bumps is provided. The substrate has a first surface and a first circuit layer, wherein the first surface has a chip disposing area and an electrical connection area, and the first circuit layer is embedded in the first surface. The photo imageable dielectric layer is disposed on the electrical connection area and has a plurality of openings, wherein parts of the first circuit layer is exposed by the openings. The conductive bumps are disposed at the openings respectively and connected to the first circuit layer, wherein a side surface of each of the conductive bumps is at least partially covered by the photo imageable dielectric layer. In addition, a manufacturing method of the circuit board is also provided.

Abstract translation: 提供了包括基板，可光致成像介电层和多个导电凸块的电路板。 基板具有第一表面和第一电路层，其中第一表面具有芯片布置区域和电连接区域，并且第一电路层嵌入在第一表面中。 可光致成像介电层设置在电连接区域上并具有多个开口，其中第一电路层的部分被开口露出。 导电凸块分别设置在开口处并连接到第一电路层，其中每个导电凸块的侧表面至少部分被可光致成像介电层覆盖。 此外，还提供了电路板的制造方法。

公开(公告)号：US20170018535A1

公开(公告)日：2017-01-19

申请号：US15262304

申请日：2016-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Guk Han ,  Seok-Joon Moon ,  Beom-jun Jin

IPC: H01L25/065 ,  G11C5/06 ,  H01L21/66 ,  H01L23/00 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L25/0657 ,  G01R31/2808 ,  G01R31/2818 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C29/04 ,  G11C29/12 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H01L22/30 ,  H01L22/32 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/0912 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4912 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/181 ,  H05K1/0268 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/002 ,  H05K3/245 ,  H05K3/28 ,  H05K3/288 ,  H05K3/323 ,  H05K2201/0187 ,  H05K2201/035 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2201/10159 ,  H05K2203/162 ,  Y10T29/49117 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

Abstract translation: 提供具有印刷电路板的电子设备。 在一个实施例中，印刷电路板包括要与外部装置耦合的多个外部焊盘和用于测试电路的多个旁路焊盘。 外部焊盘被暴露，并且多个旁路焊盘中的至少一个不暴露于PCB的外表面。 还提供了使用电子设备的系统和测试电子设备的方法。

公开(公告)号：US20170013710A1

公开(公告)日：2017-01-12

申请号：US14849614

申请日：2015-09-10

Applicant: Subtron Technology Co., Ltd.

Inventor： Chin-Sheng Wang ,  Ching-Sheng Chen ,  Mei-Chin Chang ,  Ching-Ta Chen

IPC: H05K1/09 ,  H05K3/18 ,  H05K1/11

CPC classification number: H05K1/09 ,  H05K1/111 ,  H05K3/181 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2203/072

Abstract: A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.

Abstract translation: 电路板包括基板，图案化铜层，含磷化学镀钯层，无电镀钯层和浸镀金层。 图案化铜层设置在基板上。 含磷化学镀钯层设置在图案化的铜层上，其中，在含磷化学镀钯层中，磷的重量百分比为4〜6％，钯的重量百分比为 在94％至96％的范围内。 无电镀钯层配置在含磷化学镀钯层上，其中，在化学镀钯层中，钯的重量百分比为99％以上。 浸镀金层设置在化学镀钯层上。

公开(公告)号：US20160358965A1

公开(公告)日：2016-12-08

申请号：US15241741

申请日：2016-08-19

Applicant: OLYMPUS CORPORATION

Inventor： Takuro SUYAMA ,  Takahiro SHIMOHATA

IPC: H01L27/146 ,  H01L31/0203 ,  H01L31/02

CPC classification number: H01L27/14632 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/14687 ,  H01L31/02005 ,  H01L31/0203 ,  H01L2924/0002 ,  H04N5/2253 ,  H04N5/335 ,  H05K1/028 ,  H05K3/0052 ,  H05K3/363 ,  H05K2201/0187 ,  H05K2201/0382 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/09472 ,  H05K2201/09909 ,  H01L2924/00

Abstract: An image pickup apparatus is an image pickup apparatus including: an image pickup device including a plurality of electrode pads provided in a row on an outer peripheral portion of a light-receiving surface on which a light-receiving section is formed, the plurality of electrode pads being connected to the light-receiving section; and a wiring board including a plurality of inner leads connected to respective electrode pads, wherein each of the inner leads includes a distal end portion, a bent portion and a rear end portion, the distal end portion is connected to the corresponding electrode pad, the bent portion includes a first bent portion having a recess shape relative to the light-receiving surface and a second bent portion having a protruding shape relative to the light-receiving surface, and the rear end portion is disposed in parallel with a side face of the image pickup device.

Abstract translation: 图像拾取装置是一种图像拾取装置，包括：图像拾取装置，包括在其上形成有光接收部分的受光表面的外周部分上设置成一行的多个电极焊盘，所述多个电极 焊盘连接到光接收部分; 以及布线基板，其具有与各个电极焊盘连接的多个内部引线，其中，所述内部引线中的每一个包括前端部，弯曲部和后端部，所述前端部与相应的电极焊盘连接， 弯曲部分包括相对于光接收表面具有凹槽形状的第一弯曲部分和相对于光接收表面具有突出形状的第二弯曲部分，并且后端部分与第二弯曲部分 图像拾取装置。