公开(公告)号：US20050257957A1

公开(公告)日：2005-11-24

申请号：US11131130

申请日：2005-05-16

Applicant: Kaluk Vasoya

Inventor： Kaluk Vasoya

IPC: H05K1/11 ,  H05K1/16 ,  H05K3/00 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46

CPC classification number: H05K3/4641 ,  H05K1/115 ,  H05K3/0005 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4638 ,  H05K2201/0281 ,  H05K2201/0323 ,  H05K2201/068 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Printed wiring boards and methods of manufacturing printed wiring boards are disclosed. In one aspect of the invention, the printed wiring boards include electrically conductive constraining cores having at least one resin filled channel. The resin filled channels perform a variety of functions that can be associated with electrical isolation and increased manufacturing yields.

Abstract translation: 公开了印刷电路板和制造印刷电路板的方法。 在本发明的一个方面，印刷电路板包括具有至少一个树脂填充通道的导电约束芯。 填充树脂的通道执行各种功能，可以与电气隔离和增加的制造产量相关联。

公开(公告)号：US20040212971A1

公开(公告)日：2004-10-28

申请号：US10828307

申请日：2004-04-21

Applicant: FUJI XEROX CO., LTD.

Inventor： Daisuke Iguchi

IPC: H05K007/06

CPC classification number: H05K1/0251 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/12042 ,  H05K1/0222 ,  H05K1/0231 ,  H05K1/0245 ,  H05K1/115 ,  H05K1/162 ,  H05K3/3447 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/0949 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09809 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a printed circuit board of the invention, a first signal wiring layer, a first ground layer, a second ground layer and a second signal wiring layer are laminated via an insulating material. A first signal wiring is formed on the first signal wiring layer and a second signal wiring is formed on the second signal wiring layer. The two signal wirings are connected via a first through hole. The conductive first ground layer and the conductive second ground layer are connected via a second through hole. The second through hole is insulated from the first through hole and formed so as to surround the first through hole.

Abstract translation: 在本发明的印刷电路板中，通过绝缘材料层叠第一信号布线层，第一接地层，第二接地层和第二信号布线层。 第一信号布线形成在第一信号布线层上，第二信号布线形成在第二信号布线层上。 两个信号布线通过第一通孔连接。 导电第一接地层和导电第二接地层经由第二通孔连接。 第二通孔与第一通孔绝缘并形成为围绕第一通孔。

公开(公告)号：US20030019663A1

公开(公告)日：2003-01-30

申请号：US10252058

申请日：2002-09-23

Inventor： Hidetaka Shigi ,  Naoya Kitamura ,  Masashi Nishiki ,  Tetsuya Yamazaki ,  Takehiko Hasebe ,  Masayuki Kyooi ,  Yukio Maeda

IPC: H05K007/06

CPC classification number: H05K3/403 ,  H01L2224/16237 ,  H05K1/056 ,  H05K3/045 ,  H05K3/42 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/09636 ,  H05K2201/09645 ,  H05K2201/09809 ,  H05K2201/09854

Abstract: A multi-layer wiring substrate capable of high density packaging, and a method of manufacturing the same, in which a carrier substrate, in which through holes can be easily formed in high density corresponding substantially to a pitch of connecting terminals in a semiconductor chip, and build-up layers are formed on the substrate with the application of a conventional build-up technique. When the build-up technique for repeatedly forming insulating layers and wiring layers on a carrier substrate is used to manufacture a multi-layer wiring substrate, the carrier substrate is formed in the following manner. First, an insulating resin layer is formed in a copper foil, in which a plurality of first windows are regularly provided, to cover the copper foil, and the resin layer fills the interior of the windows. Subsequently, second windows of a particular shape are provided in regions of layers of the insulating resin filled in the windows, and independent conducting paths are formed through the second windows to extend from front sides of the second windows to back sides thereof. The conducting paths are formed radially to be spaced a substantially equal distance from centers of the respective second windows.

Abstract translation: 能够进行高密度封装的多层布线基板及其制造方法，其中可以容易地以高密度形成通孔，其基本上对应于半导体芯片中的连接端子的间距， 并且通过应用常规的堆积技术在基板上形成堆积层。 当在载体基板上重复形成绝缘层和布线层的叠层技术用于制造多层布线基板时，载体基板以下列方式形成。 首先，在铜箔中形成绝缘树脂层，其中规则地设有多个第一窗口以覆盖铜箔，树脂层填充窗户的内部。 随后，将特定形状的第二窗口设置在填充在窗户中的绝缘树脂的层的区域中，并且通过第二窗口形成独立的导电路径，以从第二窗口的前侧延伸到其后侧。 导电路径径向地形成为与相应的第二窗口的中心基本相等的距离。

公开(公告)号：US20230422412A1

公开(公告)日：2023-12-28

申请号：US18244182

申请日：2023-09-08

Applicant: TOPPAN INC.

Inventor： Akihiro HAYASHI ,  Masahito TANABE ,  Tetsuyuki TSUCHIDA

IPC: H05K3/46 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H05K3/42 ,  H05K1/11

CPC classification number: H05K3/4655 ,  H01L24/16 ,  H01L24/73 ,  H01L24/32 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H05K3/429 ,  H05K1/116 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2924/15174 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09636

Abstract: A multilayer wiring board includes two or more layers laminated together, each layer includes an insulating resin layer having a first surface and a second surface, and a conductor layer. The insulating resin layer includes a first recess that is open to the first surface, a groove section that is open to the first surface, and a second recess that is open to the second surface and communicates with one or more of the first recesses. Each insulating resin layer is integrally formed in a thickness direction thereof. The conductor layer includes a land portion and a wiring portion filling the first recess and the groove section, and a via portion protruding from the first surface at a position of the land portion. The via portion protruding from the first surface of the insulating resin layer fills a recess of another insulating resin layer adjacent to the first surface.

公开(公告)号：US11778731B2

公开(公告)日：2023-10-03

申请号：US17503988

申请日：2021-10-18

Applicant: Raytheon Company

Inventor： Thanh Tran ,  David G. Haedge ,  Alton Moore ,  Paul Ingerson

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0228 ,  H05K1/0245 ,  H05K1/112 ,  H05K1/114 ,  H05K1/0251 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09636 ,  H05K2201/09672 ,  H05K2201/09718

Abstract: A multi-layer printed circuit board having a first landing pad in a first layer and along a first axis arranged to receive a positive signal and a second landing pad in the first layer and along a second axis that is spaced away from the first axis longitudinally in the first layer and where the second landing pad arranged to receive a negative signal. A first buried in a second layer and along the first axis is spaced away from the first landing pad along the first axis. A second buried in the second layer and along the second axis is spaced away from the second landing pad along the second axis. A first signal connector provides a first electrical connection between the first landing pad and the second buried via and a second signal connector provides a second electrical connection between the second landing pad and the first buried via.

公开(公告)号：US20180279476A1

公开(公告)日：2018-09-27

申请号：US15916807

申请日：2018-03-09

Applicant: FUJITSU LIMITED

Inventor： Taiki UEMURA ,  Taiji SAKAI ,  Hideki KITADA

IPC: H05K1/14 ,  H05K1/11 ,  H05K3/32 ,  H05K3/40 ,  H05K1/18

CPC classification number: H05K1/145 ,  H01R12/712 ,  H05K1/115 ,  H05K1/14 ,  H05K1/144 ,  H05K1/181 ,  H05K3/0094 ,  H05K3/32 ,  H05K3/3436 ,  H05K3/4038 ,  H05K2201/041 ,  H05K2201/042 ,  H05K2201/09636 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/10515

Abstract: An electronic apparatus includes a first circuit board, a stacked circuit that is provided on the first circuit board through first coupling terminals and has a structure in which arithmetic elements and memory elements are stacked through inter-element coupling terminals and to which a signal is inputted from the first circuit board, and a second circuit board that is provided on the stacked circuit through second coupling terminals and to which a result of processing is outputted from the stacked circuit, wherein a number of the first coupling terminals and a number of the second coupling terminals are smaller than that of the inter-element coupling terminals.

公开(公告)号：US09722012B1

公开(公告)日：2017-08-01

申请号：US15255412

申请日：2016-09-02

Applicant: QUALCOMM Incorporated

Inventor： Priyatharshan Pathmanathan ,  Devarshi Patel ,  Dennis Allen Northgrave ,  Kyle Roberts

IPC: G11C11/40 ,  G11C11/24 ,  H01L49/02 ,  H01L23/498 ,  H01L27/108 ,  G11C11/401

CPC classification number: H01L28/40 ,  G11C7/02 ,  G11C11/401 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/00 ,  H01L27/108 ,  H01L28/00 ,  H05K1/0216 ,  H05K1/0228 ,  H05K1/116 ,  H05K1/162 ,  H05K2201/09636

Abstract: An electrical device including a structure having a plurality of dielectric layers, the structure further having a plurality of vertical electrical connections extending from a top layer of the dielectric layers to a bottom layer of the dielectric layers, a first vertical electrical connection of the plurality of vertical electrical connections including a first capacitive structure that extends in a plane perpendicular to a vertical dimension of the vertical electrical connection, wherein the first capacitive structure is disposed on a first dielectric layer of the plurality of dielectric layers, wherein the first dielectric layer is below the top layer, and a second vertical electrical connection of the plurality of vertical electrical connections including a second capacitive structure extending in the plane and disposed on the first dielectric layer.

公开(公告)号：US20160360618A1

公开(公告)日：2016-12-08

申请号：US14778027

申请日：2014-12-26

Applicant: INTEL CORPORATION

Inventor： Adel A. ELSHERBINI ,  Aleksandar ALEKSOV ,  Sasha N. Oster ,  Shawna M. LIFF

IPC: H05K1/11 ,  H05K3/30 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

CPC classification number: H05K1/115 ,  H01L23/58 ,  H01L25/16 ,  H01L2924/0002 ,  H05K1/0284 ,  H05K1/0286 ,  H05K1/144 ,  H05K1/181 ,  H05K3/303 ,  H05K3/368 ,  H05K2201/042 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09963 ,  H05K2201/10037 ,  H05K2201/10128 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10583 ,  H01L2924/00

Abstract: An apparatus including a substrate including a first side and an opposite second side; at least one first circuit device on the first side of the substrate, at least one second device on the second side of the substrate; and a support on the second side of the substrate, the support including interconnections connected to the at least one first and second circuit device, the support having a thickness dimension operable to define a dimension from the substrate greater than a thickness dimension of the at least one second circuit device. A method including disposing at least one first circuit component on a first side of a substrate; disposing at least one second circuit component on a second side of the substrate; and coupling a support to the substrate, the substrate defining a dimension from the substrate greater than a thickness dimension of the at least one second circuit component.

Abstract translation: 一种装置，包括：基板，包括第一侧和相对的第二侧; 在衬底的第一侧上的至少一个第一电路器件，在衬底的第二侧上的至少一个第二器件; 以及在所述基板的第二侧上的支撑件，所述支撑件包括连接到所述至少一个第一和第二电路装置的互连件，所述支撑件具有可操作以从所述基板限定大于所述至少一个第一和第二电路装置的厚度尺寸的尺寸的厚度尺寸 一秒电路装置。 一种方法，包括在衬底的第一侧上布置至少一个第一电路部件; 在所述基板的第二侧上布置至少一个第二电路部件; 以及将支撑件耦合到所述衬底，所述衬底限定来自所述衬底的尺寸大于所述至少一个第二电路部件的厚度尺寸。

公开(公告)号：US20160249456A1

公开(公告)日：2016-08-25

申请号：US14993523

申请日：2016-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyeok YOUN ,  Jaehyung CHO ,  Myungkyoon CHUNG

IPC: H05K1/18

CPC classification number: H05K1/115 ,  H05K1/0216 ,  H05K2201/09609 ,  H05K2201/09636

Abstract: An electronic device with a reduced noise may include a printed circuit board and a signal creating unit mounted on the printed circuit board and configured to create at least one signal. The electronic device may also include at least one power via configured to connect a power terminal of the signal creating unit with a main power line disposed in the printed circuit board. The electronic device further includes at least one ground via configured to connect a ground terminal of the signal creating unit with a main ground disposed in the printed circuit board. In this electronic device, the ground via is disposed in parallel with the power via.

Abstract translation: 具有降低噪声的电子设备可以包括印刷电路板和安装在印刷电路板上并被配置为创建至少一个信号的信号产生单元。 电子设备还可以包括至少一个功率通路，其被配置为将信号生成单元的电源端子与布置在印刷电路板中的主电力线连接。 电子设备还包括至少一个接地通路，其经配置以将信号产生单元的接地端与设置在印刷电路板中的主地相连。 在该电子设备中，接地通孔与电源通路并联设置。

公开(公告)号：US09192044B2

公开(公告)日：2015-11-17

申请号：US13862038

申请日：2013-04-12

Applicant: CANON KABUSHIKI KAISHA

Inventor： Seiji Hayashi ,  Takuya Kondo ,  Shoji Matsumoto

IPC: H05K1/16 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K1/02 ,  H01L23/498

CPC classification number: H05K1/0216 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/48227 ,  H05K1/0228 ,  H05K1/0242 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/114 ,  H05K1/116 ,  H05K1/14 ,  H05K1/141 ,  H05K1/162 ,  H05K1/18 ,  H05K2201/0939 ,  H05K2201/09418 ,  H05K2201/09454 ,  H05K2201/09463 ,  H05K2201/09636 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734

Abstract: First and second signal wiring patterns are formed in a first conductor layer. A first electrode pad electrically connected to the first signal wiring pattern through a first via and a second electrode pad electrically connected to the second signal wiring pattern through a second via are formed in a second conductor layer as a surface layer. A third conductor layer is disposed between the first conductor layer and the second conductor layer with an insulator interposed between those conductor layers. A first pad electrically connected to the first via is formed in the third conductor layer. The first pad includes an opposed portion which overlaps the second electrode pad as viewed in a direction perpendicular to the surface of a printed board and which is opposed to the second electrode pad through intermediation of the insulator. This enables reduction of crosstalk noise caused between the signal wirings.

Abstract translation: 第一和第二信号布线图案形成在第一导体层中。 通过第一通孔电连接到第一信号布线图案的第一电极焊盘和通过第二通孔电连接到第二信号布线图案的第二电极焊盘形成在作为表面层的第二导体层中。 第三导体层设置在第一导体层和第二导体层之间，绝缘体插在这些导体层之间。 电连接到第一通孔的第一焊盘形成在第三导体层中。 第一焊盘包括与垂直于印刷电路板的表面的方向观察的与第二电极焊盘重叠并且通过绝缘体与第二电极焊盘相对的相对部分。 这使得能够减少在信号布线之间引起的串扰噪声。