公开(公告)号：US09894770B2

公开(公告)日：2018-02-13

申请号：US14453953

申请日：2014-08-07

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Doo Hwan Lee

IPC: H05K1/18 ,  H05K7/10 ,  H05K7/12 ,  H01R9/00 ,  H05K1/16 ,  H05K1/11 ,  H05K3/40 ,  H01L21/56

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L2224/04105 ,  H05K1/114 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4007 ,  H05K2201/10 ,  H05K2201/10022 ,  H05K2201/1003 ,  Y10T29/49146

Abstract: Disclosed is an embedded electronic component which can improve reliability of connection with external wiring and efficiency of an embedding process by including: a contact pad provided on at least one surface of a body portion and made of a conductive material; a first insulating layer for covering the at least one surface of the body portion; a first pad in contact with a surface of the contact pad and made of a conductive material; a rearrangement portion provided on a surface of the first insulating layer to be in contact with the first pad; a second pad provided on the surface of the first insulating layer to be in contact with the rearrangement portion; and a second insulating layer having an opening to expose a portion of the second pad while covering the first insulating layer, the first pad, the rearrangement portion, and the second pad.

公开(公告)号：US20170171978A1

公开(公告)日：2017-06-15

申请号：US14964575

申请日：2015-12-10

Applicant: Industrial Technology Research Institute

Inventor： Shu-Jung Yang ,  Yu-Lin Chao ,  Heng-Chieh Chien ,  Chun-Kai Liu

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/46 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/185 ,  H01L29/02 ,  H05K1/186 ,  H05K3/4605 ,  H05K2201/10 ,  H05K2201/10166

Abstract: A power module and a manufacturing method thereof are provided, and the power module includes a carrier substrate, an interconnection layer, a first chip, a second chip, a ceramic bonding substrate, a top interconnection layer and a lead frame. The interconnection layer is disposed on the carrier substrate. The first chip and the second chip are disposed on the interconnection layer, and electrically connected to the interconnection layer. The ceramic bonding substrate is disposed on the interconnection layer, and is disposed in between the first chip and the second chip so as to separate the first chip from the second chip. The top interconnection layer is disposed on the ceramic bonding substrate, covers the first chip and the second chip, and is electrically connected to the first chip and the second chip. The lead frame is disposed on the top interconnection layer and electrically connected to the top interconnection layer.

公开(公告)号：US20160234932A1

公开(公告)日：2016-08-11

申请号：US14990978

申请日：2016-01-08

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kazuhiro OSHIMA ,  Hiroharu YANAGISAWA ,  Kazuhiro KOBAYASHI ,  Katsuya FUKASE ,  Ken MIYAIRI

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/036 ,  H05K1/02 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/0366 ,  H05K1/111 ,  H05K1/181 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/4682 ,  H05K2201/01 ,  H05K2201/0183 ,  H05K2201/10

Abstract: A circuit board includes an insulating layer including first and second insulator films, a first wiring layer embedded in the first insulator film and including pads and first wiring patterns exposed from the first insulator film, and a second wiring layer including second wiring patterns formed on the second insulator film and via wirings penetrating the insulating layer and electrically connecting the second wiring patterns to the first wiring layer. The first insulator film is made of a reinforcement-free resin that includes no reinforcing member. The second insulator film is made of a reinforcing member impregnated with a resin.

Abstract translation: 电路板包括绝缘层，包括第一绝缘膜和第二绝缘膜，第一布线层嵌入第一绝缘膜中，并且包括焊盘和从第一绝缘膜露出的第一布线图案，第二布线层包括形成在第一绝缘膜上的第二布线图案 第二绝缘体膜和穿过绝缘层的通孔布线，并将第二布线图案电连接到第一布线层。 第一绝缘膜由无增强树脂制成，不含增强材料。 第二绝缘膜由浸渍有树脂的加强构件制成。

公开(公告)号：US20160170928A1

公开(公告)日：2016-06-16

申请号：US14569041

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Vladimir Tamarkin ,  Wayne Genetti ,  David Schweitzer

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F1/16 ,  G06F1/185 ,  G06F1/186 ,  G06F13/4022 ,  G06F13/409 ,  G06F2213/0026 ,  H01R12/716 ,  H01R12/721 ,  H01R12/722 ,  H01R12/727 ,  H01R12/73 ,  H01R12/737 ,  H05K1/0296 ,  H05K1/145 ,  H05K3/308 ,  H05K5/0286 ,  H05K7/1422 ,  H05K2201/10

Abstract: Some embodiments include apparatus and methods having a circuit board, a device located on the circuit board, a first Peripheral Component Interconnect Express (PCIe) connector located on the circuit board and coupled to the device, and a second PCIe connector located on the circuit board and coupled to the device. The first PCIe connector is arranged to couple to a first connector of an additional circuit board. The second PCIe connector is arranged to couple to a second connector of the additional circuit board.

Abstract translation: 一些实施例包括具有电路板的装置和方法，位于电路板上的装置，位于电路板上并耦合到该装置的第一外围组件互连Express（PCIe）连接器，以及位于电路板上的第二PCIe连接器 并耦合到该设备。 第一PCIe连接器布置成耦合到附加电路板的第一连接器。 第二PCIe连接器布置成耦合到附加电路板的第二连接器。

公开(公告)号：US20160021753A1

公开(公告)日：2016-01-21

申请号：US14802139

申请日：2015-07-17

Applicant: IBIDEN CO., LTD.

Inventor： Mitsuhiro TOMIKAWA ,  Koji ASANO

IPC: H05K1/18 ,  H05K3/00 ,  H05K3/30 ,  H05K3/46 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K3/4697 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/0206 ,  H05K1/162 ,  H05K1/185 ,  H05K3/3436 ,  H05K3/4644 ,  H05K2201/10 ,  H05K2201/10045 ,  H05K2201/10416 ,  H01L2924/00014

Abstract: A circuit substrate includes a core substrate having a cavity penetrating through the substrate, a combined component accommodated in the cavity of the substrate, a first build-up layer laminated on first surface of the substrate and including an insulating layer such that the insulating layer is covering the cavity, a second build-up layer laminated on second surface of the substrate and including an insulating layer such that the insulating layer is covering the cavity, and a filling resin filling gap formed between the cavity and combined component accommodated in the cavity of the substrate. The combined component includes an electronic component and a metal block, the electronic component has terminal surface on side facing the first surface of the substrate, and the metal block is superposed to surface of the electronic component on the opposite side of the electronic component with respect to the terminal surface.

Abstract translation: 电路基板包括具有穿透基板的空腔的芯基板，容纳在基板的空腔中的组合部件，层叠在基板的第一表面上并且包括绝缘层的第一累积层，使得绝缘层为 覆盖空腔，层叠在基板的第二表面上的第二堆叠层，并且包括绝缘层，使得绝缘层覆盖空腔;以及填充树脂填充间隙，其形成在容纳在空腔中的空腔和组合部件之间 底物。 组合部件包括电子部件和金属块，电子部件具有面向基板的第一表面的端面，并且金属块与电子部件的相对侧的电子部件的表面重叠 到终端表面。

公开(公告)号：US20150327369A1

公开(公告)日：2015-11-12

申请号：US14760982

申请日：2013-01-18

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Yasuaki Seki ,  Tomoyuki Nagata ,  Mitsuaki Toda

IPC: H05K1/18 ,  H05K3/00 ,  H05K3/46 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K1/186 ,  H01L23/5226 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/92144 ,  H05K1/0206 ,  H05K1/0222 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/185 ,  H05K1/188 ,  H05K3/0017 ,  H05K3/0035 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09827 ,  H05K2201/10 ,  H05K2203/063 ,  H05K2203/1461 ,  Y10T156/10

Abstract: A device embedded substrate (20), includes: an insulation layer (12) including an insulation resin material; an electric or electronic device (4) embedded in the insulation layer (12); a terminal (15) serving as an electrode included in the device (4); a conductor pattern (18) formed on the surface of the insulation layer (12); and a conducting via (21) for electrically connecting the conductor pattern (18) and the terminals (15) with each other. The conducting via (21) is made up of a large-diameter section (21a) having a large diameter and a small-diameter section (21b) having a smaller diameter than that of the large-diameter section (21a), in order starting from the conductor pattern (18) toward the terminal (15). A stepped section (17) is formed between the large-diameter section (21a) and the small-diameter section (21b). The large-diameter section (21a) is formed so as to penetrate a sheet-shaped glass cloth (11) disposed in the insulation layer (12).

Abstract translation: 一种器件嵌入式衬底（20），包括：绝缘层（12），包括绝缘树脂材料; 嵌入所述绝缘层（12）中的电气或电子设备（4）; 用作包括在所述装置（4）中的电极的端子（15）; 形成在所述绝缘层（12）的表面上的导体图案（18）; 以及用于将导体图案（18）和端子（15）彼此电连接的导电通孔（21）。 导电通孔（21）由大直径的大直径部分（21a）和直径小于大直径部分（21a）直径的小直径部分（21b）构成，以便顺序起动 从导体图案（18）朝向端子（15）。 在大直径部分（21a）和小直径部分（21b）之间形成有阶梯部分（17）。 大直径部分21a形成为穿透设置在绝缘层12中的片状玻璃布11。

公开(公告)号：US20150264810A1

公开(公告)日：2015-09-17

申请号：US14636356

申请日：2015-03-03

Applicant: FUJITSU LIMITED

Inventor： Shunji BABA ,  Manabu WATANABE ,  Kenji FUKUZONO ,  Satoshi OHSAWA ,  Tetsuro YAMADA ,  Akihiro WAKABAYASHI ,  Yasushi MASUDA ,  Yohei MIURA

IPC: H05K1/11 ,  H05K3/30 ,  H05K3/10 ,  H05K1/18

CPC classification number: H05K1/115 ,  H01L23/3675 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/167 ,  H01L2924/19041 ,  H01L2924/19106 ,  H05K1/0263 ,  H05K1/11 ,  H05K1/144 ,  H05K1/184 ,  H05K1/185 ,  H05K3/22 ,  H05K3/325 ,  H05K3/40 ,  H05K3/4046 ,  H05K2201/0311 ,  H05K2201/042 ,  H05K2201/045 ,  H05K2201/10 ,  H05K2201/10189 ,  H05K2201/10303 ,  H05K2201/10659 ,  H05K2201/10666 ,  H05K2201/10878 ,  H05K2201/10901 ,  H05K2203/176 ,  Y10T29/4913 ,  Y10T29/49147

Abstract: A circuit board includes: a substrate; a through hole formed in the substrate; and a connection terminal provided in the through hole; wherein the connection terminal includes a pedestal portion provided within the through hole and a pin which is provided at a center of the pedestal portion and extends from the pedestal portion toward a first surface of the substrate, so that a first end portion protrudes from the first surface.

Abstract translation: 电路板包括：基板; 形成在基板中的通孔; 以及设置在通孔中的连接端子; 其中，所述连接端子包括设置在所述通孔内的基座部分和设置在所述基座部分的中心并且从所述基座部朝向所述基板的第一表面延伸的销，使得所述第一端部从所述第一端部突出， 表面。

公开(公告)号：US20150237733A1

公开(公告)日：2015-08-20

申请号：US14700204

申请日：2015-04-30

Applicant: AT & S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFT

Inventor： Johannes Stahr ,  Markus Leitgeb

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/185 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/14 ,  H05K1/144 ,  H05K1/181 ,  H05K1/186 ,  H05K3/4623 ,  H05K3/4697 ,  H05K2201/041 ,  H05K2201/042 ,  H05K2201/043 ,  H05K2201/045 ,  H05K2201/0723 ,  H05K2201/09036 ,  H05K2201/09072 ,  H05K2201/09618 ,  H05K2201/10 ,  H05K2201/10083 ,  H05K2201/10151 ,  Y10T29/49126 ,  Y10T29/49144

Abstract: A printed circuit board having two completed printed circuit board elements which consists of a plurality of interconnected plies or layers, wherein at least one printed circuit board element has a cutout or depression containing the component to be integrated on one of the printed circuit board elements or in the cutout of the at least one printed circuit board element, and the printed circuit board elements are connected with the component being accommodated in the cutout, as a result of which it is possible to obtain secure and reliable accommodation of the component in the printed circuit board. Furthermore, a printed circuit board of this type also contains an electronic component integrated therein.

Abstract translation: 一种印刷电路板，具有由多个相互连接的层或层构成的两个完整的印刷电路板元件，其中至少一个印刷电路板元件具有切口或凹陷，所述切口或凹陷包含待集成在其中一个印刷电路板元件上的部件或 在所述至少一个印刷电路板元件的切口中，并且所述印刷电路板元件与容纳在所述切口中的所述部件连接，由此可以获得所述部件在所述印刷电路板元件中的可靠和可靠的容纳 电路板。 此外，这种印刷电路板还包含集成在其中的电子部件。

公开(公告)号：US20150163916A1

公开(公告)日：2015-06-11

申请号：US14452785

申请日：2014-08-06

Applicant: Mitsubishi Electric Corporation

Inventor： Taichi OBARA ,  Rei YONEYAMA ,  Takami OTSUKI ,  Eiju SHITAMA

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3735 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L2224/32225 ,  H01L2924/19105 ,  H05K1/11 ,  H05K1/111 ,  H05K1/186 ,  H05K1/188 ,  H05K3/3442 ,  H05K2201/09072 ,  H05K2201/09745 ,  H05K2201/10 ,  H05K2201/10174 ,  H05K2201/1059 ,  H05K2201/10636 ,  H05K2201/10651 ,  H05K2201/10674 ,  H05K2201/10689 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic component mounting device includes an insulating substrate having a metal pattern formed thereon and a MELF electronic component. The MELF electronic component is fitted into a first receiving portion configured with the metal pattern and the insulating substrate exposed from a lacking portion of the metal pattern. The electronic component mounting device further includes a conductive member formed between the MELF electronic component and the metal pattern, and the conductive member is not formed between the MELF electronic component and the insulating substrate.

Abstract translation: 电子部件安装装置包括其上形成有金属图案的绝缘基板和MELF电子部件。 MELF电子部件装配到由金属图案构成的第一接收部分和从金属图案的缺少部分露出的绝缘基板。 电子部件安装装置还包括形成在MELF电子部件和金属图案之间的导电部件，并且在MELF电子部件和绝缘基板之间不形成导电部件。

公开(公告)号：US20150049447A1

公开(公告)日：2015-02-19

申请号：US14460587

申请日：2014-08-15

Applicant: Point Engineering Co., Ltd.

Inventor： Bum Mo Ahn ,  Seung Ho Park ,  Kyoung Ja Yun

IPC: H05K3/00 ,  H05K3/46 ,  H05K1/18

CPC classification number: H05K3/0052 ,  H01L33/48 ,  H01L33/62 ,  H01L2924/0002 ,  H05K1/183 ,  H05K2201/09718 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2201/10 ,  H05K2201/10106 ,  H05K2201/10121 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A base substrate which prevents burrs generated during the cutting process includes: multiple conductive layers stacked in one direction with respect to the base substrate; at least one insulation layer being alternately stacked with said conductive layers and electrically separating said conductive layers; and a through-hole penetrating said base substrate covering said insulation layer at the contact region where said cut surface and said insulation layer meet during the cutting of said base substrate in accordance with a predetermined region of the chip substrate. A method of manufacturing the base substrate includes alternately stacking conductive layers and insulation layers and forming a through-hole.

Abstract translation: 防止在切割过程中产生的毛刺的基底基板包括：相对于基底基板沿一个方向堆叠的多个导电层; 至少一个绝缘层与所述导电层交替堆叠并电分离所述导电层; 以及根据所述芯片基板的预定区域，在切割所述基底基板期间，在所述切割面和所述绝缘层相接触的接触区域处覆盖所述绝缘层的通孔。 制造基底基板的方法包括交替地堆叠导电层和绝缘层并形成通孔。