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公开(公告)号：KR101878931B1
公开(公告)日：2018-07-17
申请号：KR1020150088941
申请日：2015-06-23
Applicant: 한국전자통신연구원
IPC: H01L29/872 , H01L29/47
CPC classification number: H01L21/0228 , H01L23/291 , H01L23/3178 , H01L29/2003 , H01L29/205 , H01L29/66212 , H01L29/872
Abstract: 반도체소자의제1 질화물반도체층은기판상에제공되고, 제2 질화물반도체층은제1 질화물반도체층상에제공되고, 제1 오믹메탈및 제2 오믹메탈은제2 질화물반도체층상에제공되고, 리세스영역은제1 오믹메탈과제2 오믹메탈사이의제2 질화물반도체층내에제공되고, 패시베이션층은제1 오믹메탈의측면및 리세스영역의하부면과측면을덮고, 쇼트키전극은제1 오믹메탈상에제공되고, 리세스영역의내부로연장된다.
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公开(公告)号：KR1020170000423A
公开(公告)日：2017-01-03
申请号：KR1020150088941
申请日：2015-06-23
Applicant: 한국전자통신연구원
IPC: H01L29/872 , H01L29/47
CPC classification number: H01L21/0228 , H01L23/291 , H01L23/3178 , H01L29/2003 , H01L29/205 , H01L29/66212 , H01L29/872
Abstract: 반도체소자의제1 질화물반도체층은기판상에제공되고, 제2 질화물반도체층은제1 질화물반도체층상에제공되고, 제1 오믹메탈및 제2 오믹메탈은제2 질화물반도체층상에제공되고, 리세스영역은제1 오믹메탈과제2 오믹메탈사이의제2 질화물반도체층내에제공되고, 패시베이션층은제1 오믹메탈의측면및 리세스영역의하부면과측면을덮고, 쇼트키전극은제1 오믹메탈상에제공되고, 리세스영역의내부로연장된다.
Abstract translation: 半导体器件的第一氮化物半导体层设置在衬底上，第二氮化物半导体层设置在第一氮化物半导体层上，第一欧姆金属和第二欧姆金属设置在第二氮化物半导体层上，凹部 在所述第一欧姆金属和所述第二欧姆金属之间的所述第二氮化物半导体层中设置钝化层，所述钝化层覆盖所述第一欧姆金属的一侧，并且所述钝化层覆盖所述凹部区域的底表面和侧面，并且所述第一欧姆金属 金属并延伸到凹陷区域中。
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公开(公告)号：KR102248808B1
公开(公告)日：2021-05-10
申请号：KR1020180046336
申请日：2018-04-20
Applicant: 한국전자통신연구원
Inventor： 안호균 , 신민정 , 김정진 , 김해천 , 도재원 , 민병규 , 윤형섭 , 이형석 , 임종원 , 장성재 , 정현욱 , 조규준 , 강동민 , 김동영 , 김성일 , 이상흥 , 이종민 , 지홍구
IPC: H01L29/778 , H01L29/66 , H01L21/762 , H01L21/027
Abstract: 제 1 반도체층과제 2 반도체층사이에절연층이매립된기판, 상가기판을관통하는관통홀, 상기관통홀은상기제 1 반도체층을관통하는제 1 홀, 및상기제 1 홀의바닥면으로부터상기절연층및 상기제 2 반도체층을관통하는제 2 홀을포함하고, 상기관통홀 내에배치되는에피층, 상기제 2 홀내에배치되어상기에피층의일면과접하는드레인전극, 및상기에피층의다른일면상에배치되는소스전극및 게이트전극을포함하는반도체소자를제공한다.
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公开(公告)号：KR101758082B1
公开(公告)日：2017-07-17
申请号：KR1020130166516
申请日：2013-12-30
Applicant: 한국전자통신연구원
IPC: H01L29/66 , H01L29/47 , H01L21/02 , H01L21/283 , H01L21/321 , H01L29/20 , H01L29/778
CPC classification number: H01L21/3212 , H01L21/0254 , H01L21/283 , H01L21/28575 , H01L21/28581 , H01L29/2003 , H01L29/41766 , H01L29/452 , H01L29/66462 , H01L29/7786
Abstract: 본발명의질화물반도체소자의제조방법에관한것으로제 1 및제 2 질화물반도체층들이차례로적층된성장기판상에복수의전극들을형성하는것, 상기각각의전극들상에상부금속층들을형성하는것, 상기성장기판을제거하여상기제 1 질화물반도체층의하면을노출하는것 및상기노출된제 1 질화물반도체층의하면상에제 3 질화물반도체층및 하부금속층을차례로형성하는것을포함하는질화물반도체소자의제조방법이제공된다.
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公开(公告)号：KR1020130066071A
公开(公告)日：2013-06-20
申请号：KR1020110132746
申请日：2011-12-12
Applicant: 한국전자통신연구원
CPC classification number: G02B1/005 , G02B1/02 , G03F7/0002
Abstract: PURPOSE: A photochromic photonic crystal structure and a manufacturing method of the same are provided to improve a photochromic property using an asymmetrical monomer. CONSTITUTION: A monomer includes a second layer greater than a first layer and a fourth layer that is greater than a third layer. The second and fourth layers include a horizontal unit extended to a horizontal direction. An asymmetrical monomer is repeatedly arranged on the substrate leaving a fixed gap to a first direction which is a horizontal direction of the substrate and is stacked to a second direction which is perpendicular to the first direction.
Abstract translation: 目的：提供光致变色光子晶体结构及其制造方法，以提高使用不对称单体的光致变色性能。 构成：单体包括大于第一层的第二层和大于第三层的第四层。 第二层和第四层包括向水平方向延伸的水平单元。 不对称单体重复地布置在基板上，留下与基板的水平方向相对的第一方向的固定间隙，并且与第一方向垂直的第二方向堆叠。
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Patent Agency Ranking
公开(公告)号：KR1020140079091A
公开(公告)日：2014-06-26
申请号：KR1020120148675
申请日：2012-12-18
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/7787 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/51 , H01L29/518 , H01L29/66462 , H01L29/7786
Abstract: A field effect transistor is provided. The transistor includes: an active layer and a capping layer which are successively stacked on a substrate; a source ohmic electrode and a drain ohmic electrode which are separated from each other on the capping layer; and a gate electrode which is arranged on the substrate between the source ohmic electrode and the drain ohmic electrode, penetrates the capping layer, and is connected to the active layer. The gate electrode includes a leg part which has a narrow width and is connected to the active layer, and the head part which has a wider width compared to the leg part and is located on the leg part. The leg part of the gate electrode on both end parts of the gate electrode in a direction of extending the gate electrode is narrower than the head part of the gate electrode of the residual part, and is wider than the leg part.
Abstract translation: 提供场效应晶体管。 晶体管包括：有源层和覆盖层，其依次层叠在基板上; 在覆盖层上彼此分离的源欧姆电极和漏极欧姆电极; 并且在源欧姆电极和漏极欧姆电极之间设置在基板上的栅极电极穿过封盖层，并连接到有源层。 栅电极包括具有窄宽度并连接到有源层的脚部，并且头部与腿部相比具有较宽的宽度并且位于腿部上。 栅电极的延伸栅电极方向的两端部的栅极电极的腿部比残留部分的栅电极的头部窄，并且比腿部部分宽。
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公开(公告)号：KR101596079B1
公开(公告)日：2016-02-22
申请号：KR1020120062664
申请日：2012-06-12
Applicant: 한국전자통신연구원
IPC: H01L21/336 , H01L29/78
Abstract: 별도의리소그라피공정과그에따른추가적인공정단계없이전계전극을형성함으로써제조비용을낮추고소자의안정성및 생산성을향상시킬수 있는전계효과트랜지스터및 그제조방법을제공한다. 본발명의일 실시예에의한전계효과트랜지스터의제조방법은, 기판상에활성층, 캡층, 오믹금속층및 절연막을순차적으로형성하는단계; 상기절연막상에다층의감광막을형성하는단계; 상기다층의감광막을패터닝하여게이트전극을위한제 1 개구부및 전계전극을위한제 2 개구부를포함하는감광막패턴을형성하는단계; 상기감광막패턴을식각마스크로이용하여상기절연막을식각하되, 상기제 1 개구부를통해상기캡층이노출되도록상기제 1 개구부내의절연막을더욱깊게식각하는단계; 상기제 1 개구부를통해절연막이식각되어노출된캡층을식각하여게이트리쎄스영역을형성하는단계; 및상기게이트리쎄스영역과, 상기식각된절연막상에금속을증착하여게이트-전계전극층을형성하는단계를포함한다.
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公开(公告)号：KR1020150077737A
公开(公告)日：2015-07-08
申请号：KR1020130166516
申请日：2013-12-30
Applicant: 한국전자통신연구원
IPC: H01L29/66 , H01L29/47 , H01L21/02 , H01L21/283 , H01L21/321 , H01L29/20 , H01L29/778
CPC classification number: H01L21/3212 , H01L21/0254 , H01L21/283 , H01L21/28575 , H01L21/28581 , H01L29/2003 , H01L29/41766 , H01L29/452 , H01L29/66462 , H01L29/7786 , H01L29/475 , H01L29/778
Abstract: 본발명의질화물반도체소자의제조방법에관한것으로제 1 및제 2 질화물반도체층들이차례로적층된성장기판상에복수의전극들을형성하는것, 상기각각의전극들상에상부금속층들을형성하는것, 상기성장기판을제거하여상기제 1 질화물반도체층의하면을노출하는것 및상기노출된제 1 질화물반도체층의하면상에제 3 질화물반도체층및 하부금속층을차례로형성하는것을포함하는질화물반도체소자의제조방법이제공된다.
Abstract translation: 本发明涉及一种制造氮化物半导体器件的方法。 提供了一种制造氮化物半导体器件的方法，其包括在生长衬底上形成电极，其中连续堆叠第一和第二氮化物半导体层，在每个电极上形成上部金属层，将第一氮化物半导体层的下表面暴露于第一氮化物半导体层的下表面 去除生长衬底，以及在暴露的第一氮化物半导体层的下表面上形成第三氮化物半导体层和下金属层。
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公开(公告)号：KR1020140076110A
公开(公告)日：2014-06-20
申请号：KR1020120144273
申请日：2012-12-12
Applicant: 한국전자통신연구원
IPC: H01L21/78 , H01L21/301
CPC classification number: H01L29/808 , H01L21/76898 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/432 , H01L29/454 , H01L29/66462 , H01L29/7786
Abstract: A semiconductor device and a method for manufacturing the same are provided. The method for manufacturing the semiconductor device comprises the steps of: forming devices including a source electrode, a drain electrode and a gate electrode on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked; etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode; conformally forming a ground interconnection on the back surface of the substrate having the via-hole; forming a protective layer on the front surface of the substrate; and cutting the substrate to separate the devices from each other.
Abstract translation: 提供半导体器件及其制造方法。 制造半导体器件的方法包括以下步骤：在包括体硅，掩埋氧化物层，活性硅，氮化镓的衬底的前表面上形成包括源电极，漏电极和栅电极的器件 层和依次层叠的氮化铝镓层; 蚀刻所述基板的背面以形成穿透所述基板的通孔并暴露所述源电极的底表面; 在具有通孔的基板的背面上共形地形成接地互连; 在所述基板的前表面上形成保护层; 并切割基板以将装置彼此分开。
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公开(公告)号：KR1020130031771A
公开(公告)日：2013-03-29
申请号：KR1020120062664
申请日：2012-06-12
Applicant: 한국전자통신연구원
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/402 , H01L21/28114 , H01L29/42376 , H01L29/66431 , H01L29/778
Abstract: PURPOSE: A field effect transistor and a method for fabrication the same are provided to improve productivity and stability by not using a lithography process. CONSTITUTION: An active layer(31), a cap layer(32), an ohmic metal layer(33) and an insulating layer(34) are formed on a substrate(30). An insulating layer is etched by using a photoresist pattern as an etching mask. A metal is deposited on a gate recess region(37c) and the insulating layer to form a gate-electric field electrode layer(39).
Abstract translation: 目的：提供场效应晶体管及其制造方法，以通过不使用光刻工艺来提高生产率和稳定性。 构成：在基板（30）上形成有源层（31），盖层（32），欧姆金属层（33）和绝缘层（34）。 通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻绝缘层。 金属沉积在栅极凹部区域（37c）和绝缘层上以形成栅极 - 电场电极层（39）。
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