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91.发明公开
公开(公告)号：KR1020110020632A
公开(公告)日：2011-03-03
申请号：KR1020090078352
申请日：2009-08-24
Applicant: 성균관대학교산학협력단
IPC: G01R1/067
CPC classification number: G01R1/067 , G01R3/00 , G01R31/2879 , G01R31/2884 , G01R31/2886
Abstract: PURPOSE: A method for forming a multi layered connecting structure of a probe unit for inspecting a flat display panel and the multi layered connecting structure made by the same are provided to increase efficiency of a production process of a connecting structure. CONSTITUTION: A plurality of signal lines(31,32,33) is formed on a substrate. A short line short-circuits intervals among partial signal lines. An insulation photo resist layer(40) insulates a part except the short circuit part between a signal line and a short line.
Abstract translation: 目的：提供一种用于形成用于检查平板显示面板的探针单元和由其制成的多层连接结构的多层连接结构的方法，以提高连接结构的生产过程的效率。 构成：在基板上形成多条信号线（31,32,33）。 部分信号线之间的短线短路间隔。 绝缘光阻层（40）将短路部分以外的部分绝缘在信号线与短线之间。
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公开(公告)号：KR1020100104484A
公开(公告)日：2010-09-29
申请号：KR1020090022927
申请日：2009-03-18
Applicant: 성균관대학교산학협력단
CPC classification number: H01L2224/11472 , H01L2224/11906 , H01L2224/131 , H01L2224/45 , H01L2224/45147 , H01L2924/00014 , H01L2924/01005 , H01L2924/01014 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/10253 , H01L2224/48 , H01L2924/00012
Abstract: PURPOSE: The manufacturing method of the free lead solder bump in which the mechanical reliability is improved is that solder the front side of the formed copper post is the capping is formed in substrate. The resistance about the shear stress is increased. CONSTITUTION: A copper wire(2) is formed on the substrate(1). The photoresist layer(3) is formed on the copper wire. According to the pattern of the photoresist layer, the copper post(5) is formed on the copper wire. The photoresist layer(4) is formed in order to have the pattern of the same diameter as the diameter of the bottom part of the copper post. The solder(10) is formed so that the frontal face of upper part of the copper post be capped.
Abstract translation: 目的：提高机械可靠性的自由铅焊料凸块的制造方法是在基板上形成形成铜柱的前侧的焊料为封盖。 关于剪切应力的阻力增加。 构成：在基板（1）上形成铜线（2）。 光致抗蚀剂层（3）形成在铜线上。 根据光致抗蚀剂层的图案，铜柱（5）形成在铜线上。 形成光致抗蚀剂层（4）以具有与铜柱的底部的直径相同直径的图案。 焊料（10）被形成为使得铜柱的上部的正面被盖住。
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公开(公告)号：KR1020100011215A
公开(公告)日：2010-02-03
申请号：KR1020080072338
申请日：2008-07-24
Applicant: 성균관대학교산학협력단
CPC classification number: H01L21/76832 , H01L21/02263 , H01L21/0274 , H01L21/3213 , H01L21/76838 , H01L21/76897
Abstract: PURPOSE: A method of manufacturing a multi-layer circuit board using selective plating by forming a middle-layer is provided to manufacture a multiple layers through a simple process by selectively forming and plating an interlayer. CONSTITUTION: A metal layer is formed on the surface of a material layer, and a first protective covering pattern is formed on the surface of the metal layer. The material layer is selectively processed by anode oxidation and a first protective covering pattern is removed. An interlayer is formed on the surface from which the first protective covering was removed. The second protective covering pattern is formed on the surface of the intermediate layer. The intermediate layer is selectively etched by the second protective covering pattern.
Abstract translation: 目的：提供一种通过形成中间层制造使用选择性镀覆的多层电路板的方法，通过简单的工艺通过选择性地形成和镀覆中间层来制造多层。 构成：在材料层的表面上形成金属层，在金属层的表面上形成第一保护覆盖图案。 通过阳极氧化选择性地处理材料层，并且去除第一保护覆盖图案。 在去除了第一保护层的表面上形成中间层。 第二保护覆盖图案形成在中间层的表面上。 中间层被第二保护覆盖图案选择性地蚀刻。
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公开(公告)号：KR100934876B1
公开(公告)日：2010-01-06
申请号：KR1020080010260
申请日：2008-01-31
Applicant: 성균관대학교산학협력단
Abstract: 본 발명은 미세구조물을 형성하기 위한 몰드를 제조하는 LIGA공정에 관한 것으로, 보다 상세하게는 LIGA공정의 도금을 보다 신속하고 효율적으로 수행하도록 하는 LIGA공정의 도금방법 및 도금장치에 관한 것이다.
본 발명의 한 실시예에 따른 LIGA공정용 도금방법은, 사진공정에 의해 레지스트 구조물을 형성하고, 이 레지스트 구조물의 표면을 도금한 후에 레지스트 구조물을 제거함으로써 몰드를 형성하며, 상기 몰드를 이용하여 미세구조물을 사출하는 LIGA공정에 있어서, 분산입자가 현탁된 도금액 내에 상기 사진공정에 의해 형성된 레지스트 구조물을 배치하고, 상기 레지스트 구조물을 제1 및 제2 전극 중에서 어느 일측에 접속하는 단계; 및 상기 제1 및 제2 전극에 전류를 인가함으로써 도금액 내의 이온입자들에 의해 분산입자들을 함께 상기 레지스트 구조물의 표면에 공석시키는 단계를 포함한다.
LIGA, 복합도금-
公开(公告)号：KR1020090115348A
公开(公告)日：2009-11-05
申请号：KR1020080041160
申请日：2008-05-02
Applicant: 성균관대학교산학협력단
IPC: H01G11/86
Abstract: PURPOSE: A method for manufacturing an electric double layer capacitor electrode using a eutectic reaction is provided to simplify a manufacturing process by forming an aluminum-carbon complex electrode through the eutectic reaction of the aluminum and silicon particle. CONSTITUTION: An aluminum foil is prepared(S12). The aluminum foil is a zincated aluminum foil. The silicon particles are coated on the surface of the aluminum foil by an ink jet method(S14). The average size of the silicon particles is below 5 um. The activated carbon particles are coated on the surface of the aluminum foil(S16). The aluminum-carbon complex electrode is formed by attaching the activated carbon particles on the surface of the aluminum foil through the eutectic reaction(S18,S20).
Abstract translation: 目的：提供一种使用共晶反应制造双电层电容器电极的方法，以通过铝和硅颗粒的共晶反应形成铝 - 碳复合电极来简化制造过程。 构成：准备铝箔（S12）。 铝箔是镀锌铝箔。 通过喷墨法将硅颗粒涂覆在铝箔的表面上（S14）。 硅颗粒的平均尺寸低于5μm。 将活性炭颗粒涂布在铝箔的表面上（S16）。 通过共晶反应将活性炭颗粒附着在铝箔的表面上，形成铝 - 碳复合电极（S18，S20）。
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Patent Agency Ranking
公开(公告)号：KR1020090104378A
公开(公告)日：2009-10-06
申请号：KR1020080029778
申请日：2008-03-31
Applicant: 성균관대학교산학협력단
CPC classification number: H01L21/76838 , H01L21/31144 , H01L21/76802 , H01L23/12
Abstract: PURPOSE: A multilayer manufacturing method using the anode oxidation is provided to apply the aluminum oxide to the interlayer dielectric layer and to improve the high electrical characteristic of insulation performance. CONSTITUTION: The multilayer manufacturing method using the anode oxidation comprises as follows. The first metal layer is formed in the surface of a substrate(S1). The first circuit has the first part oxidative region and the first metal wirings by oxidizing the first metal layer partially. The interlayer dielectric layer is formed by anodizing extensively the first metal layer and the first part oxidative region(S3). The penetration hole is formed by partially etching the interlayer dielectric layer. The second metal layer is formed within the surface and penetration hole of the interlayer dielectric layer(S5). The second circuit has the second part oxidative region and the second metal wirings.
Abstract translation: 目的：提供使用阳极氧化的多层制造方法以将氧化铝施加到层间电介质层，并提高绝缘性能的高电特性。 构成：使用阳极氧化的多层制造方法如下。 第一金属层形成在基板的表面（S1）中。 第一电路通过部分氧化第一金属层而具有第一部分氧化区和第一金属布线。 通过对第一金属层和第一部分氧化区域进行阳极氧化而形成层间电介质层（S3）。 穿透孔通过部分蚀刻层间电介质层而形成。 第二金属层形成在层间介质层的表面和贯通孔内（S5）。 第二电路具有第二部分氧化区和第二金属布线。
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公开(公告)号：KR1020090037101A
公开(公告)日：2009-04-15
申请号：KR1020070102536
申请日：2007-10-11
Applicant: 성균관대학교산학협력단
IPC: H01L21/027 , H01L21/288
CPC classification number: H01L21/76874 , G03F7/42 , H01L21/0274 , H05K3/422
Abstract: A method for forming a metal pattern of a substrate is provided to directly form a pattern on a surface of a substrate without a coating process of a metal film by increasing roughness of the surface of the substrate. A predetermined pattern is formed by performing a photolithography process on a surface of a substrate(S1). The pattern is formed by a photoresist in a pattern forming step. The photoresist is made of negative AZ5214 material. The photolithography process is performed by irradiating an ultraviolet ray. A roughness of a surface of a part etched on the substrate is improved(S2). A roughness improving process is performed by a sanding process. The photoresist on the surface of the substrate is removed by performing a strip process. A selective metal pattern is formed by performing an electroless plating process(S3).
Abstract translation: 提供了形成基板的金属图案的方法，以通过增加基板的表面的粗糙度，直接在基板的表面上形成图案，而不用金属膜的涂覆处理。 通过在基板的表面上进行光刻工序来形成规定的图案（S1）。 图案由图案形成步骤中的光致抗蚀剂形成。 光致抗蚀剂由负AZ5214材料制成。 通过照射紫外线进行光刻处理。 蚀刻在基板上的部分的表面的粗糙度得到改善（S2）。 通过砂光处理进行粗糙度改善处理。 通过进行剥离处理，去除衬底表面上的光致抗蚀剂。 通过进行化学镀处理来形成选择性金属图案（S3）。
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公开(公告)号：KR1020090035963A
公开(公告)日：2009-04-13
申请号：KR1020070101019
申请日：2007-10-08
Applicant: 성균관대학교산학협력단
CPC classification number: H01L21/76897 , H01L21/3213 , H01L21/76838
Abstract: A formation method of the through hole electrode is provided to reduce the process time by growing the conductor material based on the side wall seed layer of the through hole. The through hole formation step is the step that forms one or more through holes on the substrate by using the RIE(Reactive Ion Etch) etcher etc(S1). The through hole is formed by the dry etching process. A step for forming the side wall seed layer is to form the side wall seed layer in the inner wall surface of the through hole of substrate(S2). The side wall seed layer is formed by the electroless plating process. A step for forming the coated layer is to form the coated layer including the dry film formed in the one side of substrate(S3). The coated layer is formed by the general coating progress. The though electrode is formed by filling up the conductor material including Cu etc from the side wall seed layer of the through hole to the center(S4).
Abstract translation: 提供通孔电极的形成方法，以通过基于通孔的侧壁种子层生长导体材料来缩短处理时间。 通孔形成步骤是通过使用RIE（反应离子蚀刻）蚀刻器等在基板上形成一个或多个通孔的步骤（S1）。 通孔是通过干式蚀刻工艺形成的。 用于形成侧壁种子层的步骤是在基板的通孔的内壁表面中形成侧壁种子层（S2）。 侧壁种子层通过无电镀方法形成。 形成涂层的步骤是形成包含在基材一侧形成的干膜的涂层（S3）。 涂层通过一般的涂层进行形成。 贯通电极通过从贯通孔的侧壁种子层向中央填充包括Cu等的导体材料而形成（S4）。
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公开(公告)号：KR100887557B1
公开(公告)日：2009-03-09
申请号：KR1020070086924
申请日：2007-08-29
Applicant: 성균관대학교산학협력단
IPC: H05K3/06
Abstract: 본 발명의 연성인쇄회로기판의 제조방법은 베이스 기판 상에 상기 베이스 기판의 일부가 노출되도록 마스크 필름을 형성하는 단계; 상기 노출된 베이스 기판 및 상기 마스크 필름 상에 시드금속막을 형성하는 단계; 상기 시드금속막 상에 금속막을 형성하는 단계; 및 상기 마스크 필름을 제거하여 상기 마스크 필름 상의 시드금속막 및 금속막을 제거하고, 상기 베이스 기판 상에 시드금속막 및 금속막으로 이루어진 도전성 패턴을 형성하는 단계를 포함한다. 금속막의 에칭 공정을 실시하지 않으므로, 에칭 공정으로 인한 환경유해물질의 배출을 막을 수 있고, 에칭 공정이 곤란한 범위에서도 연성인쇄회로기판을 제조할 수 있다.
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公开(公告)号：KR1020090014543A
公开(公告)日：2009-02-11
申请号：KR1020070078588
申请日：2007-08-06
Applicant: 성균관대학교산학협력단
Abstract: A method for forming high ordered aluminum anodizing oxidation holes and a method for forming magnetic recording media using the same are provided to form high ordered nano-holes regularly by controlling the formation position on the aluminium layer through a guide pattern. A method for forming high ordered aluminum anodizing oxidation holes comprises a step of selectively forming a guide pattern(14a) for guiding the forming position of anode oxidation holes formed during anode oxidation by selectively blocking aluminium area exposed on an aluminum layer(12), and a step of regularly forming a plurality of nano-holes in which alumina is formed on the outside surface by performing anode oxidation on the exposed aluminium area and controlling formation position of nano-hole(12b) according to the kind of the guide pattern masking the exposed aluminium area.
Abstract translation: 提供一种形成高阶铝阳极化氧化孔的方法以及使用其形成磁记录介质的方法，以通过引导图案控制铝层上的形成位置来规则地形成高有序纳米孔。 一种形成高阶铝阳极化氧化孔的方法，包括以下步骤：选择性地形成引导图案（14a），用于通过选择性地阻挡暴露在铝层（12）上的铝区域来引导在阳极氧化期间形成的阳极氧化孔的形成位置，以及 通过在露出的铝区域上进行阳极氧化，并且根据导电图案的种类来控制纳米孔（12b）的形成位置，从而在外表面上规则地形成多个纳米孔，其中在外表面上形成氧化铝， 暴露铝面积。
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