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    Multilayer substrate provided with layer constitution display unit
    93.
    发明专利
    Multilayer substrate provided with layer constitution display unit 审中-公开
    多层基板由层状显示单元提供

    公开(公告)号：JP2007294640A

    公开(公告)日：2007-11-08

    申请号：JP2006120209

    申请日：2006-04-25

    Applicant: Orion Denki Kk ,  オリオン電機株式会社

    Inventor： MITSUI CHIHIRO ,  SHIMADA TSUTOMU

    IPC: H05K1/02 ,  H05K3/46

    CPC classification number: H05K1/0269 ,  H05K3/4638 ,  H05K2201/09327 ,  H05K2201/09781 ,  H05K2201/09909 ,  Y10T428/24917

    Abstract: PROBLEM TO BE SOLVED: To provide a layer constitution display unit capable of easily discriminating the constitutions of respective layers in a multilayer substrate. SOLUTION: The same number of paired copper foil constituted so that two copper foils correspond to one layer as the number of layers constituting the multilayer substrate are formed on the outer layer of the multilayer substrate 2 as layer constitution discrimination marks 3. The layer constitution discrimination marks 3 are displayed by three states "covered with resist", "covered with resist and silk" and "not covered with any of resist and silk", so that six kinds of constitutions at maximum can be displayed per layer and the constitutions of respective layers of the multilayer substrate 2 can be easily discriminated. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 解决的问题：提供能够容易地区分多层基板中的各层的构成的层构造显示单元。 解决方案：作为层构成鉴别标记3，在多层基板2的外层上形成有相同数量的成对铜箔，因为构成多层基板的层的数量，两个铜箔对应于一层。 层状结构辨别标记3由“覆盖抗蚀剂”，“覆盖抗蚀剂和丝绸”和“不被抗蚀剂和丝绸覆盖”的三个状态显示，使得每层可以显示最多六种结构，并且 可以容易地区分多层基板2的各层的结构。 版权所有（C）2008，JPO＆INPIT

    Multilayer module
    94.
    发明专利
    Multilayer module 有权
    多层模块

    公开(公告)号：JP2005223332A

    公开(公告)日：2005-08-18

    申请号：JP2005026945

    申请日：2005-02-02

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： FRECH ROLAND DR ,  GARBEN BERND DR ,  KLINK ERICH ,  OGGIONI STEFANO

    IPC: H01L23/12 ,  H01L23/498 ,  H05K1/00 ,  H05K1/02

    CPC classification number: H05K1/0216 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0298 ,  H05K2201/09327 ,  H05K2201/10522 ,  H05K2201/10734

    Abstract: PROBLEM TO BE SOLVED: To increase the importance of a future microprocessor and a future computer system by decreasing power noise of intermediate frequency, by providing a semiconductor device structure for improving power noise property, and to provide a multilayer module having superior electrical characteristics accompanying reduction in the manufacturing cost, increase in wiring capability, and decrease in inductance. SOLUTION: A multilayer module comprises a top conductive layer L1 to which an electronic component is attached, a plurality of insulating layers 6, and a plurality of conductive layers L2-L8 arranged between the insulating layers. As for the conductive layers L1-L4 near the front surface of the module, two of at least three layers, a potential layer and/or a ground layer, are arranged alternately such that a signal layer is not sandwiched by the layers. Further, the multilayer module has a via, by which a corresponding signal layer, the potential layer, and the ground layer are electrically connected with each another and also with the top conductive layer L1. Further, the multilayer module has two layers of the potential layer and the ground layer, arranged alternately near the front surface, so that there is no signal layer therebetween, and a structure in which the via is not arranged in a local region for attaining the electrical effects of a solid surface. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：通过提供用于提高功率噪声性能的半导体器件结构，通过降低中频功率噪声来增加未来微处理器和未来计算机系统的重要性，并提供具有优异电气的多层模块 随着制造成本的降低，接线能力的增加和电感的降低。 解决方案：多层模块包括安装电子部件的顶部导电层L1，多个绝缘层6和布置在绝缘层之间的多个导电层L2-L8。 对于在模块前表面附近的导电层L1-L4，交替地布置至少三层中的至少三层，即电位层和/或接地层，使得信号层不被层夹在中间。 此外，多层模块具有通孔，相应的信号层，电位层和接地层彼此电连接，并且还与顶部导电层L1电连接。 此外，多层模块具有两层电位层和接地层，交替地布置在前表面附近，使得它们之间不存在信号层，并且其中通孔不被布置在局部区域中以获得 固体表面的电气效应。 版权所有（C）2005，JPO＆NCIPI

    High frequency module
    98.
    发明授权
    High frequency module 有权
    高频模块

    公开(公告)号：US09220164B2

    公开(公告)日：2015-12-22

    申请号：US14489555

    申请日：2014-09-18

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Hiromichi Kitajima

    IPC: H04M1/00 ,  H05K1/02 ,  H05K1/18 ,  H01P3/16 ,  H04M1/02

    CPC classification number: H05K1/0216 ,  H01P3/16 ,  H04M1/026 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/09327

    Abstract: A high frequency module includes a ground mounting electrode connected to a ground terminal of a component, a first ground in-plane conductor in a multilayer substrate on a portion under the component and connected to the ground mounting electrode with a first ground interlayer connecting conductor, a signal mounting electrode connected to a signal terminal of the component, and a signal in-plane conductor provided in the multilayer substrate on a portion under the first ground in-plane conductor and connected to the specific signal mounting electrode with a signal interlayer connecting conductor. The first ground in-plane conductor is between the component and the signal in-plane conductor, and the signal interlayer connecting conductor is on an outer side portion of the first ground in-plane conductor when seen from above.

    Abstract translation: 高频模块包括连接到部件的接地端子的接地安装电极，在部件下方的多个基板中的第一接地面内导体，并且与第一接地层间连接导体连接到接地安装电极， 连接到部件的信号端子的信号安装电极，以及设置在第一接地面内导体下的部分上的多层基板中的信号面内导体，并且与信号层间连接导体连接到特定信号安装电极 。 第一接地面内导体位于组件和信号面内导体之间，并且当从上方观察时，信号层间连接导体位于第一接地面内导体的外侧部分。

    FAULT CONTAINMENT ROUTING
    99.
    发明申请
    FAULT CONTAINMENT ROUTING 有权
    故障排除路由

    公开(公告)号：US20150264801A1

    公开(公告)日：2015-09-17

    申请号：US14297825

    申请日：2014-06-06

    Applicant: Honeywell International Inc.

    Inventor： Kenneth Lee Martin ,  Lucilo De La Torre ,  James Frederick Peterson ,  Jonathan Cole

    IPC: H05K1/02 ,  H05K1/11

    CPC classification number: H05K1/0237 ,  G06F17/5077 ,  H01L21/486 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/535 ,  H01L2924/0002 ,  H05K1/0218 ,  H05K1/115 ,  H05K2201/0723 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K2201/09972 ,  H01L2924/00

    Abstract: Systems and methods described herein provide for a circuit board having multiple fault containment regions therein. The circuit board includes a first fault containment region defined, at least in part, by first and second metal layers coupled to ground. The first fault containment region includes a first signal layer between the first and second metal layers, a third metal layer between the first and second metal layers, the third metal layer connected to the first signal layer to provide a return path for the first signal layer, and a fourth metal layer between the first and second metal layers, the fourth metal layer connected to the first signal layer to provide power to the first signal layer. The circuit board also includes a second fault containment region in a plurality of layers below the first fault containment region.

    Abstract translation: 本文所述的系统和方法提供了其中具有多个故障容纳区域的电路板。 电路板包括第一故障容纳区域，该第一故障容纳区域至少部分地由耦合到地面的第一和第二金属层限定。 第一故障容纳区域包括在第一和第二金属层之间的第一信号层，在第一和第二金属层之间的第三金属层，第三金属层连接到第一信号层以提供第一信号层的返回路径 以及在第一和第二金属层之间的第四金属层，第四金属层连接到第一信号层以向第一信号层提供电力。 电路板还包括在第一故障容纳区域下方的多个层中的第二故障容纳区域。

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