公开(公告)号：US20080246157A1

公开(公告)日：2008-10-09

申请号：US11732543

申请日：2007-04-03

Applicant: Qiang Richard Chen

Inventor： Qiang Richard Chen

IPC: H01L23/482 ,  H01L21/60

CPC classification number: H05K3/3442 ,  H01L27/016 ,  H01L27/13 ,  H05K1/16 ,  H05K3/366 ,  H05K3/403 ,  H05K2201/0317 ,  H05K2201/09954 ,  H05K2201/10045 ,  Y02P70/613

Abstract: A device according to various aspects of the present invention generally includes a surface mount device having a top side, a bottom side, a plurality of sidewalls, and a circuit comprising one or more layers. The device includes a first conductive surface covering a portion of one of the sidewalls for providing an input to the circuit, a second conductive surface covering a portion of one of the sidewalls for providing an output from the circuit, and a third conductive surface covering a portion of one of the sidewalls for providing an electrical ground to the circuit. When the surface mount device is mounted to a provided mounting surface, at least one layer of the circuit is orthogonal to the provided mounting surface.

Abstract translation: 根据本发明的各个方面的装置通常包括具有顶侧，底侧，多个侧壁和包括一个或多个层的电路的表面安装装置。 所述装置包括覆盖所述侧壁之一的一部分以提供所述电路的输入的第一导电表面，覆盖所述侧壁之一的一部分以提供来自所述电路的输出的第二导电表面，以及覆盖所述侧壁的第三导电表面 所述侧壁之一的一部分用于向所述电路提供电接地。 当表面安装装置安装到所提供的安装表面时，电路的至少一层与所提供的安装表面正交。

公开(公告)号：US20060017133A1

公开(公告)日：2006-01-26

申请号：US11188723

申请日：2005-07-26

Applicant: Kiyoshi Oi ,  Yasuyoshi Horikawa ,  Akihito Takano

Inventor： Kiyoshi Oi ,  Yasuyoshi Horikawa ,  Akihito Takano

IPC: H01L29/00

CPC classification number: H05K1/185 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/82 ,  H01L2224/18 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/141 ,  H05K1/16 ,  H05K3/20 ,  H05K3/4602 ,  H05K2201/0317 ,  H05K2201/10045 ,  H05K2203/016

Abstract: An electronic part-containing element used by being incorporated in an electronic device, in which the electronic part-containing element comprises an insulating support member which does not take part in the constitution of the electronic device but is removed in the process of producing the electronic device, and a circuit module supported by the support member, and the circuit module contains one or more electronic parts, each in the form of a thin film, therein and has connection terminals for the electronic part at least on the surface thereof that comes into contact with the support member.

Abstract translation: 一种电子部件容纳元件，其通过结合在电子装置中而被使用，其中所述电子部件容纳元件包括绝缘支撑构件，所述绝缘支撑构件不参与所述电子装置的构造，但在制造所述电子装置的过程中被去除 装置和由支撑构件支撑的电路模块，并且电路模块包含一个或多个薄膜形式的电子部件，其中至少在其表面上具有用于电子部件的连接端子 与支撑构件接触。

公开(公告)号：US06946733B2

公开(公告)日：2005-09-20

申请号：US10640073

申请日：2003-08-13

Applicant: David Poole ,  Terry R. Bloom ,  Richard Cooper

Inventor： David Poole ,  Terry R. Bloom ,  Richard Cooper

IPC: H01C1/14 ,  H05K1/02 ,  H05K1/14 ,  H05K1/16 ,  H05K3/28 ,  H05K3/34 ,  H01L23/48

CPC classification number: H05K1/0268 ,  H01C1/14 ,  H05K1/141 ,  H05K1/167 ,  H05K3/28 ,  H05K3/3436 ,  H05K2201/10045

Abstract: A ball grid array package that can be readily tested before or after mounting to a printed circuit board. The ball grid array includes a substrate having a top surface and a bottom surface. Several conductive pads are located on the top surface. Several passive circuit elements are located on the top surface between the conductive pads. An insulative coating is placed on top of the passive circuit elements and the substrate. The insulative coating has openings over the conductive pads. The openings are adapted to be accessible by an electrical probe. Conductive vias extend through the substrate between the top and bottom surfaces. The vias electrically connect with the conductive pad on the top surface. Several conductive balls are located on the bottom surface. Each conductive ball is electrically connected to one of the vias.

Abstract translation: 一种球栅阵列封装，可在安装到印刷电路板之前或之后轻松测试。 球栅阵列包括具有顶表面和底表面的基底。 几个导电垫位于顶部表面。 几个无源电路元件位于导电焊盘之间的顶表面上。 绝缘涂层放置在无源电路元件和基板的顶部。 绝缘涂层在导电焊盘上有开口。 这些开口适于通过电探针来接近。 导电通孔在顶表面和底表面之间延伸通过基底。 通孔与顶表面上的导电垫电连接。 几个导电球位于底面。 每个导电球电连接到一个通孔。

公开(公告)号：US06476695B1

公开(公告)日：2002-11-05

申请号：US09578691

申请日：2000-05-26

Applicant: Masumi Nakamichi

Inventor： Masumi Nakamichi

IPC: H01P308

CPC classification number: H05K1/167 ,  H05K1/0237 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H05K2201/10045 ,  H05K2203/1461

Abstract: A high frequency module is provided with a resistor array layer with interconnections, in which a plurality of resistor elements having a prescribed resistance value are formed as an array, and in which an interconnection pattern for providing electrical connection to each resistor element is formed in advance. Additionally, a capacitor array layer with interconnection in which a plurality of capacitor elements having a prescribed capacitance value are formed as an array and an interconnection pattern for providing electrical connection to each capacitor element is also formed in advance for later use. A desired circuit constant is obtained by providing interconnections among the plurality of resistor elements and among the plurality of capacitor elements, respectively, in any given combination by simply modifying the respective interconnection patterns instead of the entire module. With this configuration, a high frequency module of a more compact and lighter type which facilitates design modification is provided at a low cost.

Abstract translation: 高频模块设置有具有互连的电阻器阵列层，其中具有规定电阻值的多个电阻元件形成为阵列，并且其中预先形成用于提供与每个电阻器元件的电连接的互连图案 。 此外，具有互连的电容器阵列层，其中具有规定的电容值的多个电容器元件形成为阵列，并且还预先形成用于提供与每个电容器元件的电连接的互连图案供稍后使用。 通过仅通过简单地修改相应的互连图案而不是整个模块，分别在多个电阻元件之间和多个电容器元件之间分别提供互连来获得期望的电路常数。 利用这种配置，以低成本提供了便于设计修改的更紧凑和更轻型的高频模块。

公开(公告)号：US06353540B1

公开(公告)日：2002-03-05

申请号：US08860181

申请日：1997-07-10

Applicant: Yutaka Akiba ,  Yasunori Narizuka ,  Hirayoshi Tanei ,  Naoya Kitamura

Inventor： Yutaka Akiba ,  Yasunori Narizuka ,  Hirayoshi Tanei ,  Naoya Kitamura

IPC: H05K116

CPC classification number: H05K1/0246 ,  H01L23/5383 ,  H01L23/552 ,  H01L25/16 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0227 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/092 ,  H05K1/113 ,  H05K1/115 ,  H05K1/162 ,  H05K1/167 ,  H05K3/403 ,  H05K3/4053 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/4652 ,  H05K3/467 ,  H05K9/0039 ,  H05K2201/0209 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09354 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/09663 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10045 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2224/0401

Abstract: A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation off a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure, a circuit board using it, and a method of manufacturing the circuit board are also disclosed. Parallel plate lines in which the Q-value of the stray capacitance between solid layers viewed from the power supply layer and ground layer is equivalently reduced and which are matchedly terminated by forming a structure in which a resistor (resistor layer) and another ground layer are provided in addition to the power supply layer and the ground layer on a multilayered circuit board. A closed shield structure is also disclosed. This invention can remarkably suppress unwanted radiation by absorbing the potential fluctuation (resonance) which occurs in a power supply loop by equivalently reducing the Q-value of the stray capacitance, absorbing the standing wave by the parallel plate lines matchedly terminated and, closing and shielding the parallel plate lines.

Abstract translation: 一种低EMI电路，其通过将电源层上的电位波动相对于在切换IC器件等而发生的接地层的电位变化转换为基底中的焦耳热，而不使用任何部件作为对策来实现高安装密度 针对EMI。 还公开了其结构，使用它的电路板以及制造电路板的方法。 从电源层和接地层观察的固体层之间的杂散电容的Q值的平行板线等效地减少，并且通过形成其中电阻器（电阻层）和另一接地层的结构匹配地终止 除了在多层电路板上的电源层和接地层之外提供。 还公开了封闭的屏蔽结构。 本发明通过吸收电源回路中发生的电位波动（谐振）可以显着地抑制不期望的辐射，通过等效地降低杂散电容的Q值，吸收平行板线匹配终止的驻波，闭合屏蔽 平行板线。

公开(公告)号：US20020021561A1

公开(公告)日：2002-02-21

申请号：US09892746

申请日：2001-06-28

Inventor： Hiroshi Yamauchi ,  Minoru Yamamoto

IPC: H05K007/06 ,  H05K001/16

CPC classification number: H05K3/3442 ,  H01C1/012 ,  H01G4/40 ,  H05K2201/10045 ,  H05K2201/10537 ,  Y02P70/613

Abstract: Three or more, or two or more types of electronic components are formed on one substrate, and these electronic components form an aggregated planar surface on a surface of the substrate to attain the above object.

Abstract translation: 在一个基板上形成三个以上或两个以上的电子部件，这些电子部件在基板的表面上形成聚集的平面，以达到上述目的。

公开(公告)号：US06194990B1

公开(公告)日：2001-02-27

申请号：US09268956

申请日：1999-03-16

Applicant: Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

Inventor： Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

IPC: H01C101

CPC classification number: H05K1/167 ,  H05K3/0023 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09845 ,  H05K2201/10045 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: A thin-film metal resistor (44) suitable for a multilayer printed circuit board (12), and a method for its fabrication. The resistor (44) generally has a multilayer construction, with the individual layers (34, 38) of the resistor (44) being self-aligned with each other so that a negative mutual inductance is produced that very nearly cancels out the self-inductance of each resistor layer (34, 38). As a result, the resistor (44) has a very low net parasitic inductance. In addition, the multilayer construction of the resistor (44) reduces the area of the circuit board (12) required to accommodate the resistor (44), and as a result reduces the problem of parasitic interactions with other circuit elements on other layers of the circuit board (12).

Abstract translation: 适用于多层印刷电路板（12）的薄膜金属电阻（44）及其制造方法。 电阻器（44）通常具有多层结构，其中电阻器（44）的各个层（34,38）彼此自对准，使得产生负的互感，其几乎抵消了自感 的每个电阻层（34,38）。 结果，电阻器（44）具有非常低的净寄生电感。 此外，电阻器（44）的多层结构减小了容纳电阻器（44）所需的电路板（12）的面积，结果减少了与其他层上的其它电路元件的寄生相互作用的问题 电路板（12）。

公开(公告)号：US5621619A

公开(公告)日：1997-04-15

申请号：US445237

申请日：1995-05-19

Applicant: Lewis L. Seffernick ,  Neal F. Thomas

Inventor： Lewis L. Seffernick ,  Neal F. Thomas

IPC: H01C1/01 ,  H01C13/02 ,  H01C17/00 ,  H01C17/28 ,  H05K3/30 ,  H05K3/34 ,  H01R9/00

CPC classification number: H05K3/303 ,  H01C13/02 ,  H01C17/006 ,  H05K3/3442 ,  H05K2201/09909 ,  H05K2201/10022 ,  H05K2201/10045 ,  H05K2201/10454 ,  H05K2201/10568 ,  H05K2201/10696 ,  H05K2201/10984 ,  H05K2203/167 ,  H05K3/3452 ,  Y02P70/613

Abstract: A resistor network is disclosed which is suited for surface mount which does not incorporate wire terminations. The network is fabricated entirely from cermet, ceramic, and solder, yet will absorb thermal stresses normally associated with circuitry energization when properly mounted upon a substrate. This is accomplished by controlling the formation of solder bumps and simultaneously controlling the mounted distance between those bumps and a wiring substrate upon which the network is mounted. Additionally, the network may be formed to be either a SIP or DIP configuration, depending upon whether an additional groove is incorporated into the termination side of the substrate. Two alternative embodiments are also disclosed which incorporate various features of the invention.

Abstract translation: 公开了一种适用于不包含电线终端的表面安装的电阻器网络。 网络完全由金属陶瓷，陶瓷和焊料制成，但是当正确安装在基板上时，它将吸收通常与电路通电相关的热应力。 这是通过控制焊料凸点的形成并同时控制这些凸起之间的安装距离和安装网络的布线基板来实现的。 另外，取决于附加的沟槽是否被结合到衬底的端接侧中，网络可以形成为SIP或DIP配置。 还公开了两个替代实施例，其包括本发明的各种特征。

公开(公告)号：US4331949A

公开(公告)日：1982-05-25

申请号：US175954

申请日：1980-08-07

Applicant: Yoshii Kagawa

Inventor： Yoshii Kagawa

IPC: H01C7/00 ,  H01C13/02 ,  H01L27/01 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H01C1/012

CPC classification number: H05K1/167 ,  H01C13/02 ,  H01C7/003 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/10045

Abstract: A thick film printed circuit in which a plurality of electrode patterns are disposed with approximately equal spaced intervals between one another, resistance patterns having approximately equal widths are mounted between adjacent electrode patterns of said plurality of electrode patterns, and an identical shaped resistance pattern to said resistance pattern is provided so as to align in parallel with at least one of said resistance patterns, whereby exact divided potential can be obtained.

Abstract translation: 一种厚膜印刷电路，其中多个电极图案彼此间隔开大致相等的间隔设置，具有大致相等宽度的电阻图案安装在所述多个电极图案的相邻电极图案之间，并且与所述 提供电阻图案以与所述电阻图案中的至少一个平行地对准，从而可以获得精确的分割电位。

公开(公告)号：US4127934A

公开(公告)日：1978-12-05

申请号：US813069

申请日：1977-07-05

Applicant: John E. Bartley ,  Orville R. Penrod ,  Lawrence D. Radosevich

Inventor： John E. Bartley ,  Orville R. Penrod ,  Lawrence D. Radosevich

IPC: H01L23/50 ,  H01G4/236 ,  H01L23/498 ,  H05K1/03 ,  H05K1/09 ,  H05K1/14 ,  H05K1/16 ,  H05K3/34 ,  H05K3/40 ,  H05K3/32

CPC classification number: H05K3/3405 ,  H01L23/49811 ,  H05K1/167 ,  H01L2924/0002 ,  H05K1/0272 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/141 ,  H05K1/162 ,  H05K2201/09163 ,  H05K2201/10045 ,  H05K2201/1034 ,  H05K2201/10924 ,  H05K3/403 ,  Y10T29/49101 ,  Y10T29/49151 ,  Y10T29/53174

Abstract: An electrical circuit device having a substrate including circuit components on at least one side thereof and a plurality of through openings in the substrate. Terminal leads are positioned in the openings each with a deformation intermediate the ends of the leads and spaced internally of the opening from a soldered area at the juncture of the exposed portion of the leads and the termination edge of the substrate. Two methods of assembly of leads to the substrate are also disclosed.

Abstract translation: 一种电路装置，其具有在至少一个侧面上包括电路元件的基板和该基板中的多个通孔。 端子引线定位在开口中，每个开口具有在引线的端部之间的中心的变形，并且在引线的暴露部分和基板的终端边缘的接合处的焊接区域处与开口的内部隔开。 还公开了将引线组装到衬底的两种方法。