公开(公告)号：KR1020120077415A

公开(公告)日：2012-07-10

申请号：KR1020100139354

申请日：2010-12-30

Applicant: 삼성전자주식회사 ,  연세대학교 산학협력단

Inventor： 박경배 ,  류명관 ,  이광희 ,  선종백 ,  배중현 ,  정웅희 ,  이상윤 ,  김현재

IPC: H01B5/14 ,  H01L29/786

CPC classification number: H01L21/02554 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/7869

Abstract: PURPOSE: A composition for forming an oxide semiconductor, an inkjet printing process using the same, and an electronic device including the oxide semiconductor thin film are provided to obtain an oxide semiconductor without defects through an inkjet printing process by using a composition containing a fixed quantity of sol stabilizer. CONSTITUTION: A gate electrode(20) and a gate insulation layer(21) covering the gate electrode are formed on a substrate(10). A channel layer(22) corresponding to the gate electrode is formed on the gate insulation layer. A source electrode(24a) and a drain electrode(24b) are formed on both sides of the channel layer. An etch stopper is formed between the source electrode and the drain electrode. The gate electrode controls the current flow between the source electrode and the drain electrode.

Abstract translation: 目的：提供一种用于形成氧化物半导体的组合物，使用其的喷墨印刷方法和包括氧化物半导体薄膜的电子器件，以通过使用含有固定量的组合物通过喷墨印刷方法获得无缺陷的氧化物半导体 的溶胶稳定剂。 构成：在基板（10）上形成覆盖栅电极的栅电极（20）和栅极绝缘层（21）。 在栅绝缘层上形成对应于栅电极的沟道层（22）。 源极电极（24a）和漏电极（24b）形成在沟道层的两侧。 在源电极和漏电极之间形成蚀刻停止层。 栅电极控制源电极和漏电极之间的电流。

公开(公告)号：KR1020110106225A

公开(公告)日：2011-09-28

申请号：KR1020100106851

申请日：2010-10-29

Applicant: 삼성전자주식회사

Inventor： 박경배 ,  류명관 ,  선종백 ,  이상윤 ,  구본원

IPC: H01L29/786 ,  G02F1/136

CPC classification number: H01L29/7869 ,  H01L29/4908 ,  H01L29/66742

Abstract: 게이트 전극, 상기 게이트 전극과 중첩하며 제1 금속 산화물을 포함하는 반도체, 상기 게이트 전극과 상기 반도체 사이에 위치하며 제2 금속 산화물을 포함하는 게이트 절연막, 그리고 상기 반도체와 전기적으로 연결되어 있는 소스 전극 및 드레인 전극을 포함하고, 상기 제1 금속 산화물 및 상기 제2 금속 산화물은 하나 이상의 금속을 공통적으로 포함하는 박막 트랜지스터 및 그 제조 방법과 상기 박막 트랜지스터를 포함하는 표시 장치를 제공한다.

公开(公告)号：KR1020090128888A

公开(公告)日：2009-12-16

申请号：KR1020080054863

申请日：2008-06-11

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 정지심 ,  이우철 ,  권장연 ,  박현상 ,  한상면 ,  류명관 ,  김태상 ,  박경배 ,  유병욱 ,  손경석 ,  한민구

IPC: G09G3/30 ,  G09G3/32 ,  G09G3/20 ,  H01L51/50

CPC classification number: G09G3/3233 ,  G09G3/2037 ,  G09G3/2081 ,  G09G2300/0842 ,  H01L27/3244 ,  H01L2027/11879 ,  H01L2227/323

Abstract: PURPOSE: An organic light emitting display device and a driving method thereof are provided to display the images with various colors by the gray scale of various steps by inserting at least one additional bit signal for an additional sub frame. CONSTITUTION: A driving transistor(T2) switches the current supply to an OLED by an image signal. A current controller includes a plurality of current control transistors(T3,T4) controlling an amount of currents to the OLED. A driving transistor operates in a linear region. Current control transistors operate at a saturation region. A storage capacitor stores an image signal. A switching transistor stores the image signal in a storage capacitor.

Abstract translation: 目的：提供一种有机发光显示装置及其驱动方法，通过插入附加子帧的至少一个附加位信号，通过各种步骤的灰度显示各种颜色的图像。 构成：驱动晶体管（T2）通过图像信号将电流源切换到OLED。 电流控制器包括控制到OLED的电流量的多个电流控制晶体管（T3，T4）。 驱动晶体管在线性区域中工作。 电流控制晶体管在饱和区域工作。 存储电容器存储图像信号。 开关晶体管将图像信号存储在存储电容器中。

公开(公告)号：KR1020090095315A

公开(公告)日：2009-09-09

申请号：KR1020080020585

申请日：2008-03-05

Applicant: 삼성전자주식회사

Inventor： 박경배 ,  김태상 ,  이상윤 ,  류명관 ,  권장연 ,  유병욱 ,  손경석 ,  정지심

IPC: C09K13/04 ,  H01L21/306 ,  H01L29/786

CPC classification number: C09K13/04 ,  C23F1/16 ,  H01L21/306 ,  H01L29/41733 ,  H01L29/7869

Abstract: An etchant for the source of an oxide semiconductor thin film transistor and a drain electrode, and a method for preparing an oxide semiconductor thin film transistor by using the etchant are provided to prevent the back etching of an oxide semiconductor and the dissolution of an oxide semiconductor and to improve etching rate. An etchant for the source of an oxide semiconductor thin film transistor and a drain electrode comprises hydrogen peroxide, ammonium hydroxide, and water. A manufacturing method of an oxide semiconductor thin film transistor comprises the steps of forming a gate on a substrate(110), and forming a gate insulating layer(114) on the substrate so as to cover the gate; forming a channel layer(116) comprising an oxide semiconductor on the gate insulating layer; and forming a metal layer for the formation of a source and a drain electrode at on both surfaces of the channel layer, and pattering it by using the etchant to form a source and drain electrodes(118a,118b).

Abstract translation: 提供了用于氧化物半导体薄膜晶体管和漏极的源的蚀刻剂，以及通过使用蚀刻剂制备氧化物半导体薄膜晶体管的方法，以防止氧化物半导体的反向蚀刻和氧化物半导体的溶解 并提高蚀刻速率。 用于氧化物半导体薄膜晶体管和漏电极源的蚀刻剂包括过氧化氢，氢氧化铵和水。 氧化物半导体薄膜晶体管的制造方法包括以下步骤：在衬底（110）上形成栅极，并在衬底上形成栅极绝缘层（114）以覆盖栅极; 在所述栅极绝缘层上形成包含氧化物半导体的沟道层（116）; 以及在沟道层的两个表面上形成用于形成源极和漏极的金属层，并且通过使用蚀刻剂来形成源极和漏极以形成源极和漏极（118a，118b）。

公开(公告)号：KR1020090079696A

公开(公告)日：2009-07-22

申请号：KR1020080005854

申请日：2008-01-18

Applicant: 삼성전자주식회사 ,  성균관대학교산학협력단

Inventor： 박경배 ,  김홍범 ,  염근영 ,  이형철 ,  이상윤 ,  류명관 ,  김태상 ,  권장연 ,  손경석 ,  정지심

IPC: H05H1/26 ,  H01L21/205

CPC classification number: H01J37/3211 ,  H01J37/32183 ,  H01J37/32431 ,  H01J37/32715 ,  H01Q1/366 ,  H05H1/46 ,  H05H2001/2412 ,  H05H2001/4667 ,  H05H2001/4682

Abstract: A plasma processing apparatus having linear antennas is provided to improve density uniformity of plasma by changing a thickness of a dielectric for surrounding the linear antenna. A plasma processing apparatus having linear antennas includes a reaction chamber(110), a substrate supporting plate(120), linear antennas(132), an RF power source(138), and a dielectric(142). The substrate supporting plate is installed in a lower side of the inside of the reaction chamber in order to support a substrate to be processed. The linear antennas are used for inducing electric field to generate electric field. The linear antennas are installed in parallel to each other at an upper side of the inside of the reaction chamber. The RF power source is connected to the linear antennas in order to supply RF power to the linear antennas. The dielectric is formed to surround each of the linear antennas. The thickness of the dielectric is gradually reduced from a RF power input terminal of each linear antenna to a grounding terminal(132b).

Abstract translation: 提供具有线性天线的等离子体处理装置，通过改变用于包围线状天线的电介质的厚度来改善等离子体的密度均匀性。 具有线性天线的等离子体处理装置包括反应室（110），基板支撑板（120），线性天线（132），RF电源（138）和电介质（142）。 基板支撑板安装在反应室内侧的下侧，以便支撑待处理的基板。 线性天线用于感应电场以产生电场。 线性天线在反应室内部的上侧彼此平行地安装。 RF电源连接到线性天线，以便向线性天线提供RF功率。 电介质形成为围绕每个线性天线。 电介质的厚度从每个线性天线的RF功率输入端逐渐减小到接地端子（132b）。

公开(公告)号：KR1020090057690A

公开(公告)日：2009-06-08

申请号：KR1020070124383

申请日：2007-12-03

Applicant: 삼성전자주식회사

Inventor： 손경석 ,  이상윤 ,  류명관 ,  김태상 ,  권장연 ,  박경배 ,  정지심

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L21/265

Abstract: A method for manufacturing an oxide semiconductor thin film transistor is provided to improve stability and reliability of the semiconductor thin film transistor by using an oxide semiconductor made of a channel material. A gate insulating layer(114) is formed on a substrate with a gate(112). A channel layer(116) made of the oxide semiconductor is formed on a gate insulating layer. A source electrode(118a) and a drain electrode(118b) are formed in both sides of the channel layer. The plasma process is performed to supply the oxygen to the channel layer. The protection layer covering the source and drain electrodes, and the channel layer is formed. After forming the protection layer, the thermal process is performed.

Abstract translation: 提供一种用于制造氧化物半导体薄膜晶体管的方法，以通过使用由沟道材料制成的氧化物半导体来改善半导体薄膜晶体管的稳定性和可靠性。 在具有栅极（112）的基板上形成栅极绝缘层（114）。 在栅极绝缘层上形成由氧化物半导体构成的沟道层（116）。 源极电极（118a）和漏电极（118b）形成在沟道层的两侧。 执行等离子体处理以将氧气供应至沟道层。 形成覆盖源电极和漏电极的保护层以及沟道层。 形成保护层后，进行热处理。

公开(公告)号：KR1020090010757A

公开(公告)日：2009-01-30

申请号：KR1020070074119

申请日：2007-07-24

Applicant: 삼성전자주식회사

Inventor： 정지심 ,  이상윤 ,  류명관 ,  권장연 ,  박경배

IPC: H01L29/786 ,  H01L21/20

CPC classification number: H01L21/2053 ,  H01L29/6675

Abstract: A polycrystalline silicon thin film and a method of thin film transistor applying the same are provided to obtain medium quality of a poly-crystal silicon and a amorphous silicon in order to be used in a high quality electronic product. A silicon thin film(20) is formed with high density plasma chemical vapor deposition having plasma density more than 2.00E+11cm-3 on a substrate(10). Hydrogen gas is included to reaction gas. The gas forming the silicon thin film comprises one selected from the group of Ar and He. A polycrystalline silicon thin film and a method of thin film transistor applying the same comprises a step for forming a channel region and active layer having a source region and a drain region of the both sides of the channel regions.

Abstract translation: 提供多晶硅薄膜及其应用薄膜晶体管的方法以获得多晶硅和非晶硅的介质质量，以便用于高质量的电子产品中。 在衬底（10）上形成具有大于2.00E + 11cm-3的等离子体密度的高密度等离子体化学气相沉积的硅薄膜（20）。 氢气被包含在反应气体中。 形成硅薄膜的气体包括选自Ar和He的一种。 多晶硅薄膜和施加该多晶硅薄膜的薄膜晶体管的方法包括形成具有沟道区两侧的源极区和漏极区的沟道区和有源层的步骤。

公开(公告)号：KR1020080076292A

公开(公告)日：2008-08-20

申请号：KR1020070016033

申请日：2007-02-15

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 정지심 ,  류명관 ,  권장연 ,  박경배 ,  한민구 ,  이상윤 ,  박중현 ,  한상면 ,  김선재

IPC: H01L29/786

CPC classification number: H01L29/78621 ,  H01L29/42384 ,  H01L2029/7863 ,  H01L29/78675

Abstract: A thin film transistor and a manufacturing method thereof are provided to change doping level for respective semiconductor layer regions by adjusting thickness and location of first, second, and third insulation layers. A thin film transistor comprises a lower structure(11), a semiconductor layer(12), first and second insulation layers(14a,14b), and a third insulation layer(16), and a gate electrode layer(17). The semiconductor layer includes a plurality of doped regions(12b,12c,12d) on the lower structure. The first and second insulation layers are formed on the semiconductor layer, separated from each other. The third insulation layer is formed on the first and second insulation layers. The gate electrode layer is formed on the third insulation layer between the first and second insulation layers. The width of the third insulation layer is longer than that between the first and second insulation layers and shorter than that between the left part of the first insulation layer and the right part of the second insulation layer.

Abstract translation: 提供薄膜晶体管及其制造方法，通过调整第一，第二和第三绝缘层的厚度和位置来改变各半导体层区域的掺杂水平。 薄膜晶体管包括下部结构（11），半导体层（12），第一和第二绝缘层（14a，14b）以及第三绝缘层（16）和栅电极层（17）。 半导体层包括在下部结构上的多个掺杂区域（12b，12c，12d）。 第一绝缘层和第二绝缘层形成在半导体层上，彼此分离。 第三绝缘层形成在第一和第二绝缘层上。 栅电极层形成在第一和第二绝缘层之间的第三绝缘层上。 第三绝缘层的宽度比第一绝缘层和第二绝缘层之间的宽度长，并且比第一绝缘层的左部分和第二绝缘层的右部分之间的宽度短。

公开(公告)号：KR1020080025830A

公开(公告)日：2008-03-24

申请号：KR1020060090467

申请日：2006-09-19

Applicant: 삼성전자주식회사

Inventor： 정지심 ,  김종만 ,  권장연 ,  박경배

IPC: H05B33/00 ,  H05B33/02 ,  H05B33/10

CPC classification number: H01L21/02672 ,  H01L21/02532 ,  H01L27/1277 ,  H01L27/3244

Abstract: An organic electro-luminescent display and a fabrication method thereof are provided to obtain an active layer with a low mobility and an active layer with a high mobility by obtaining different poly crystal silicon islands. An organic electro-luminescent display includes an amorphous silicon(2), a capping layer(3), a driving transistor, and a switching transistor. The capping layer is formed on the amorphous silicon and has two parts(3a,3b) having different thicknesses. The driving transistor is formed under a thick part of the capping layer and drives the organic electro-luminescent display. The switching transistor is formed under a thinner part of the capping layer and controls operation of the driving transistor.

Abstract translation: 提供一种有机电致发光显示器及其制造方法，通过获得不同的多晶硅岛获得具有低迁移率的有源层和具有高迁移率的有源层。 有机电致发光显示器包括非晶硅（2），封盖层（3），驱动晶体管和开关晶体管。 覆盖层形成在非晶硅上，并且具有不同厚度的两个部分（3a，3b）。 驱动晶体管形成在覆盖层的较厚部分的下方并驱动有机电致发光显示器。 开关晶体管形成在覆盖层的较薄部分的下方，并控制驱动晶体管的工作。

公开(公告)号：KR1020070040128A

公开(公告)日：2007-04-16

申请号：KR1020050095496

申请日：2005-10-11

Applicant: 삼성전자주식회사

Inventor： 박경배 ,  임혁 ,  타카시노구치 ,  조세영 ,  권장연

IPC: H01L29/786

Abstract: 셀프얼라인에 의한 오프셋 구조를 가지는 박막트랜지스터 및 그 제조방법에 관해 개시한다. 박막트랜지스터는 기판과; 기판 상에 형성되는 것으로 폭이 넓은 부분과 좁은 부분을 가지는 것으로 그 양측에 경사면이 형성된 돌출부를 가지는 버퍼층과; 상기 버퍼층의 돌출부상에 마련되는 채널과 돌출부의 양측에 위치하는 소스 및 드레인을 가지는 것으로 상기 돌출부의 양측 경사부에 대응하는 오프렛 구조를 가지는 반도체층과; 상기 돌출부의 상방에 마련되는 것으로 상기 돌출부의 좁은 부분에 비해 큰 폭을 가지는 게이트 절연층 및 게이트를 구비한다.
오프셋, LDD, 박막트랜지스터