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公开(公告)号：KR101735479B1
公开(公告)日：2017-05-16
申请号：KR1020150090508
申请日：2015-06-25
Applicant: 한국과학기술원
Abstract: 본발명은 SOI(semiconductor-on-insulator) 기판을준비하는단계; 스티칭(stitching) 공정을이용하여상기 SOI 기판상에복수개의픽셀형이미지센서를형성하는단계; 상기복수개의픽셀형이미지센서상에 PDMS(polydimethylsiloxane)층을형성하고, 선택적식각(dicing-by-trench) 공정을이용하여상기 SOI 기판의적어도일부를제거함으로써스탬프를형성하는단계; 상기스탬프의적어도일면상에유연기판을결합하는단계; 및상기스탬프의일부인상기 PDMS층을제거하고, 상기 PDMS층과대응되는영역에섬광체를형성하는단계;를포함하는, 플렉서블반도체방사선검출기의제조방법, 이를이용하여구현한플렉서블반도체방사선검출기및 이를포함하는방사선영상장치를제공한다.
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公开(公告)号：KR101250447B1
公开(公告)日：2013-04-08
申请号：KR1020110132858
申请日：2011-12-12
Applicant: 한국과학기술원
Abstract: PURPOSE: An MEMS device manufacturing method is provided to obtain excellent performance and shape by easily controlling the thickness of a film according to a device and obtain an MEMS device capable of utilizing an existing semiconductor process. CONSTITUTION: An MEMS device manufacturing method comprises; a step for forming a lower structure(12), a step for a chalcogenide carbon layer; a step for forming insulation-supporting layer on the chalcogenide carbon layer; a step for forming via-holes exposing the lower structure by forming an etched protection layer on the insulation-supporting layer and etching the insulation-supporting layer and the chalcogenide carbon layer; a step for forming an upper structure including a sensor(23) on an insulation-supporting layer; a step for forming one or more through-holes penetrating the insulation-supporting layer; a step for removing the chalcogenide carbon layer through the through-holes in order to arrange the upper and lower structure to be spaced.
Abstract translation: 目的：提供一种MEMS器件制造方法，通过根据器件轻松控制膜的厚度来获得优异的性能和形状，并获得能够利用现有半导体工艺的MEMS器件。 构成：MEMS器件制造方法包括： 形成下部结构（12）的步骤，硫族化物碳层的工序; 在硫族化物碳层上形成绝缘支撑层的步骤; 通过在绝缘支撑层上形成蚀刻保护层并蚀刻绝缘层和硫族化物碳层，形成露出下部结构的通孔的步骤; 在绝缘支撑层上形成包括传感器（23）的上部结构的步骤; 形成穿过绝缘支撑层的一个或多个通孔的步骤; 用于通过通孔去除硫族化物碳层以便将上部和下部结构间隔开的步骤。
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公开(公告)号：KR100746910B1
公开(公告)日：2007-08-07
申请号：KR1020060043044
申请日：2006-05-12
Applicant: 한국과학기술원
IPC: H01L21/3065
Abstract: A plasma etching apparatus and a plasma etching method are provided to enhance a surface roughness of a wafer, to prevent the generation of failure in an etching process, to improve the efficiency of the etching process, and to control variously the angle of a wafer profile. A plasma etching apparatus includes a chamber(210) for performing an etching process on a wafer(200), a gas flow unit, an upper electrode unit, and a lower electrode unit. The gas flow unit(220) is used for flowing a mixed gas of SF6 and O2 into the chamber. At this time, the flow rate of O2 is 0.8 to 1.4 times larger than that of the SF6. The upper electrode unit(230) is applied with an RF power for changing gas into plasma. The lower electrode unit(250) is applied with a bias voltage for inducing the plasma toward the wafer.
Abstract translation: 提供等离子体蚀刻装置和等离子体蚀刻方法以增强晶片的表面粗糙度，防止在蚀刻过程中产生故障，提高蚀刻过程的效率，并且各种方式控制晶片轮廓的角度 。 等离子体蚀刻设备包括用于在晶片（200）上执行蚀刻工艺的腔室（210），气体流动单元，上电极单元和下电极单元。 气流单元（220）用于使SF6和O2的混合气体流入腔室。 此时，O2的流量比SF6的流量大0.8〜1.4倍。 上电极单元（230）被施加用于将气体转变为等离子体的RF功率。 下电极单元（250）被施加用于向晶片引发等离子体的偏压。
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Patent Agency Ranking
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17.发明公开플렉서블 반도체 방사선 검출기의 제조방법, 이를 이용한 플렉서블 반도체 방사선 검출기 및 이를 포함하는 방사선 영상장치 有权使用该柔性半导体辐射探测器的柔性半导体辐射探测器的制造方法以及包括该柔性半导体辐射探测器
公开(公告)号：KR1020170001074A
公开(公告)日：2017-01-04
申请号：KR1020150090508
申请日：2015-06-25
Applicant: 한국과학기술원
Abstract: 본발명은 SOI(semiconductor-on-insulator) 기판을준비하는단계; 스티칭(stitching) 공정을이용하여상기 SOI 기판상에복수개의픽셀형이미지센서를형성하는단계; 상기복수개의픽셀형이미지센서상에 PDMS(polydimethylsiloxane)층을형성하고, 선택적식각(dicing-by-trench) 공정을이용하여상기 SOI 기판의적어도일부를제거함으로써스탬프를형성하는단계; 상기스탬프의적어도일면상에유연기판을결합하는단계; 및상기스탬프의일부인상기 PDMS층을제거하고, 상기 PDMS층과대응되는영역에섬광체를형성하는단계;를포함하는, 플렉서블반도체방사선검출기의제조방법, 이를이용하여구현한플렉서블반도체방사선검출기및 이를포함하는방사선영상장치를제공한다.
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公开(公告)号：KR101342900B1
公开(公告)日：2013-12-18
申请号：KR1020110144878
申请日：2011-12-28
Applicant: 한국과학기술원
Abstract: 본발명은나노임프린트용복제몰드에관한것으로서, 더욱상세하게는나노패턴이전사되는대상인고분자물질로부터의이형성이향상된나노임프린트용복제몰드의제조방법에관한것이다. 본발명에따르면, (a) 마스터기판에양각과음각의나노패턴을형성하여마스터몰드를제작하는단계와, (b) 상기마스터몰드상에고분자용액을도포한후 경화하여역상의나노패턴이형성된고분자몰드를제조하는단계와, (c) 상기고분자몰드를상기마스터몰드에서분리하는단계와, (d) 상기고분자몰드의역상의나노패턴상에금속층을형성하는단계를포함하는나노임프린트용복제몰드의제조방법이제공된다. 본발명에따른나노임프린트용복제몰드는나노패턴상에금속층이형성되어있거나, 단독의금속박판체로구성되어있어종래의나노임프린트용몰드에비해서이형성이우수하다. 따라서고분자물질에전사된나노패턴의품질이우수하다.
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公开(公告)号：KR1020100062502A
公开(公告)日：2010-06-10
申请号：KR1020080121159
申请日：2008-12-02
Applicant: 한국과학기술원
IPC: H01L21/8242 , H01L29/78 , H01L21/336 , H01L27/108
CPC classification number: H01L27/108 , H01L27/10826 , H01L29/1033
Abstract: PURPOSE: A capacitor-less DRAM and a method for manufacturing the same are provided to improve the hole-storage capacity due to a hole-barrier by forming a continuous germanium layers or a non-continuous dots through an ion implantation method and a heat treatment process. CONSTITUTION: A source(105), a channel, and a drain(106) are successively formed on a substrate(100). A gate insulating layer(103) is formed on the channel. A gate is formed on the gate insulating layer. A germanium layer or a germanium dot is formed in the channel. The gate insulating layer is made of a silicon oxide, a nitride film, an aluminum oxide, a hafnium oxide, or a zinc oxide.
Abstract translation: 目的：提供一种无电容器DRAM及其制造方法，以通过离子注入法和热处理形成连续锗层或非连续点来改善由于空穴阻挡引起的空穴存储能力 处理。 构成：源（105），沟道和漏极（106）依次形成在衬底（100）上。 在沟道上形成栅极绝缘层（103）。 栅极形成在栅极绝缘层上。 在通道中形成锗层或锗点。 栅极绝缘层由氧化硅，氮化物膜，氧化铝，氧化铪或氧化锌制成。
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公开(公告)号：KR1020080092603A
公开(公告)日：2008-10-16
申请号：KR1020070036124
申请日：2007-04-12
Applicant: 한국과학기술원
IPC: H01L27/108 , H01L27/115 , B82Y10/00
CPC classification number: H01L27/11551 , H01L21/28273 , H01L27/10823
Abstract: A nonvolatile DRAM(Dynamic Random Access Memory) cell with a 3-dimensional all-around gate structure, and a method for manufacturing and driving the same are provided to implement DRAM without using a capacitor through a natural floating body effect and to secure an excellent short channel effect and a punchthrough effect by forming the all-around gate structure for completely enclosing the whole surface with a gate. A nonvolatile memory unit encloses the whole surface of a part that becomes a channel of a semiconductor pillar. A gate(106) encloses the nonvolatile memory unit. A source and a drain(109,110) are respectively formed on a left and a right of the channel of the semiconductor pillar. A dielectric(101) is formed on a substrate(100). The semiconductor pillar is in parallel with the dielectric. The gate is formed on the gate. The nonvolatile memory unit includes a tunneling dielectric(103), a floating gate(104), and a control dielectric(105). The tunneling dielectric encloses the whole surface of the semiconductor pillar. The floating gate encloses the tunneling dielectric. The control dielectric encloses the floating gate.
Abstract translation: 提供具有三维全方位栅极结构的非易失性DRAM（动态随机存取存储器）单元及其制造和驱动方法，以通过自然浮体效应实现DRAM而不使用电容器并确保优异的 短沟道效应和穿透效果，通过形成用于用栅极完全包围整个表面的全面栅极结构。 非易失性存储器单元包围成为半导体柱的通道的部件的整个表面。 门（106）包围非易失性存储单元。 源极和漏极（109,110）分别形成在半导体柱的沟道的左侧和右侧。 电介质（101）形成在基板（100）上。 半导体柱与电介质平行。 门形成在门上。 非易失性存储器单元包括隧道电介质（103），浮动栅极（104）和控制电介质（105）。 隧道电介质围绕半导体柱的整个表面。 浮动栅极包围隧道电介质。 控制电介质包围浮动栅极。
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