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    A NON-SELF-ALIGNED SIGE HETEROJUNCTION BIPOLAR TRANSISTOR
    12.
    发明申请
    A NON-SELF-ALIGNED SIGE HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
    非自对准信号异相双极晶体管

    公开(公告)号：WO03001584A8

    公开(公告)日：2004-05-27

    申请号：PCT/US0219789

    申请日：2002-06-19

    Applicant: IBM

    Inventor： JAGANNATHAN BASANTH ,  JENG SHWU-JEN ,  JOHNSON JEFFREY B ,  JOHNSON ROBB A ,  LANZEROTTI LOUIS D ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

    IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/737 ,  H01L31/11

    CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

    Abstract: A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions (70) with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal (66) wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.

    Abstract translation: 一种用于制造非自对准的异质结双极晶体管的方法包括：在发射极堆叠中形成具有与多晶硅对准的PFET源极/漏极注入的非本征基极区域（70），但并不直接对准在该区域中限定的发射极开口 叠加。 这通过使发射器基座（66）比发射器开口更宽来实现。 这有利地消除了非本征基区和发射极开口之间的对准的依赖性，从而导致更少的工艺步骤，减少的热循环和改进的速度。

    Stressed channel fet with source/drain buffers
    14.
    发明专利
    Stressed channel fet with source/drain buffers 未知

    公开(公告)号：GB2500848A

    公开(公告)日：2013-10-02

    申请号：GB201312793

    申请日：2012-01-16

    Applicant: IBM

    Inventor： JOHNSON JEFFREY B ,  MURALIDHAR RAMACHANDRAN ,  OLDIGES PHILLIP J ,  ONTALUS VIOREL C ,  XIU KAI

    IPC: H01L21/8238 ,  H01L21/8234 ,  H01L27/12

    Abstract: A method for forming a stressed channel field effect transistor (FET) with source/drain buffers (501) includes etching cavities (301) in a substrate (201) on either side of a gate stack located (202/203) on the substrate; depositing source/drain buffer material (401) in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region (502) of the FET; and depositing source/drain stressor material (601) in the cavities adjacent to and over the vertical source/drain buffers.

    Isolationsstrukturen mit anstossendem SOI-Übergang und Einheiten sowie Verfahren zur Herstellung
    15.
    发明专利
    Isolationsstrukturen mit anstossendem SOI-Übergang und Einheiten sowie Verfahren zur Herstellung 未知

    公开(公告)号：DE112011103730T5

    公开(公告)日：2013-09-26

    申请号：DE112011103730

    申请日：2011-11-10

    Applicant: IBM

    Inventor： NARASIMHA SHREESH ,  ONTALUS VIOREL C ,  JOHNSON JEFFREY B ,  NAYFEH HASAN M

    IPC: H01L29/78 ,  H01L21/336

    Abstract: Eine Struktur, ein FET, ein Verfahren zum Herstellen der Struktur und zum Herstellen des FET. Die Struktur beinhaltet: eine Siliciumschicht (105; 5) auf einer vergrabenen Oxid(BOX)-Schicht (115) eines Silicium-auf-Isolator-Substrats (100); einen Graben in der Siliciumschicht, der sich von einer Oberseite der Siliciumschicht in die Siliciumschicht hinein erstreckt, wobei sich der Graben nicht bis zu der BOX-Schicht (160, 165, und 170) erstreckt, einen dotierten Bereich (155) in der Siliciumschicht zwischen der BOX-Schicht und einem Boden des Grabens und an diese angrenzend, wobei der erste dotierte Bereich bis zu einer ersten Dotierstoffkonzentration dotiert ist; eine erste epitaxiale Schicht (160) in einem Boden des Grabens, die bis zu einer zweiten Dotierstoffkonzentration dotiert ist; eine zweite epitaxiale Schicht (165) auf der ersten epitaxialen Schicht in dem Graben, die bis zu einer dritten Dotierstoffkonzentration dotiert ist; und wobei die dritte Dotierstoffkonzentration höher als die erste und zweite Dotierstoffkonzentration ist und die erste Dotierstoffkonzentration höher als die zweite Dotierstoffkonzentration ist.

    FET mit verspanntem Kanal mit Source/Drain-Puffern
    17.
    发明专利
    FET mit verspanntem Kanal mit Source/Drain-Puffern 未知

    公开(公告)号：DE112012000510T5

    公开(公告)日：2013-12-05

    申请号：DE112012000510

    申请日：2012-01-16

    Applicant: IBM

    Inventor： JOHNSON JEFFREY B ,  MURALIDHAR RAMACHANDRAN ,  OLDIGES PHILLIP J ,  ONTALUS VIOREL C ,  XIU KAI

    IPC: H01L21/336 ,  H01L21/782 ,  H01L21/8238 ,  H01L27/12

    Abstract: Ein Verfahren zum Bilden eines Feldeffekttransistors (FET) mit verspanntem Kanal mit Source/Drain-Puffern (501) beinhaltet ein Ätzen von Hohlräumen (301) in einem Substrat (201) auf beiden Seiten eines Gate-Stapels (202/203), der sich auf dem Substrat befindet; Abscheiden von Source/Drain-Puffermaterial (401) in den Hohlräumen; Ätzen des Source/Drain-Puffermaterials, um vertikale Source/Drain-Puffer neben einem Kanalbereich (502) des FET zu bilden; und Abscheiden von Source/Drain-Stressormaterial (601) in den Hohlräumen neben und über den vertikalen Source/Drain-Puffern.

    Delta monolayer dopants epitaxy for embedded source/drain silicide
    18.
    发明专利
    Delta monolayer dopants epitaxy for embedded source/drain silicide 未知

    公开(公告)号：GB2494608B

    公开(公告)日：2013-09-04

    申请号：GB201300789

    申请日：2011-06-10

    Applicant: IBM

    Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

    IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

    Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

    DELTA MONOLAYER DOPANTS EPITAXY FOR EMBEDDED SOURCE/DRAIN SILICIDE
    19.
    发明专利
    DELTA MONOLAYER DOPANTS EPITAXY FOR EMBEDDED SOURCE/DRAIN SILICIDE 未知

    公开(公告)号：SG184824A1

    公开(公告)日：2012-11-29

    申请号：SG2012075586

    申请日：2011-06-10

    Applicant: IBM

    Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

    Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).

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