公开(公告)号：DE10005774B4

公开(公告)日：2005-09-29

申请号：DE10005774

申请日：2000-02-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WERNER WOLFGANG ,  SOMMER PETER ,  KANERT WERNER

IPC: H01L29/78 ,  H01L29/872

Abstract: DMOS cell consists of DMOS transistor (11) and Schottky diode (12) which lie parallel to the source-drain path of the transistor. The source zone (6) of the transistor is in contact with a source-contact layer (7, 14) via a contact hole (8) in a gate insulating layer (9). The Schottky diode is formed in the contact hole between the source-contact layer and the drain zone (1, 2) of the transistor. Preferred Features: The source-contact layer is provided with a Schottky metallization (13) made from tungsten silicide, tantalum silicide, platinum silicide or molybdenum silicide, and has a plug (14) made from conducting polycrystalline silicon.

公开(公告)号：DE10014659C2

公开(公告)日：2002-08-01

申请号：DE10014659

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VIETZKE DIRK ,  STECHER MATTHIAS ,  SCHULZE HANS-JOACHIM ,  PERI HERMANN ,  NELLE PETER ,  PLOSS REINHARD ,  KANERT WERNER

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/32 ,  H01L29/78 ,  H01L27/08 ,  H01L23/58 ,  H01L29/06

公开(公告)号：DE102016109349A1

公开(公告)日：2017-11-23

申请号：DE102016109349

申请日：2016-05-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOERNER HEINRICH ,  ENGL REIMUND ,  MAHLER JOACHIM ,  HUETTINGER MICHAEL ,  BAUER MICHAEL ,  KANERT WERNER ,  RUEHLE BRIGITTE ,  GATTERBAUER JOHANN ,  DANGELMAIER JOCHEN ,  VELLEI ANTONIO ,  SANTOS RODRIGUEZ FRANCISCO JAVIER ,  HILLE FRANK

IPC: H01L23/18 ,  H01L21/56 ,  H01L23/26 ,  H01L23/29 ,  H01L23/31 ,  H01L23/488

Abstract: Bei diversen Ausführungsformen wird ein Chipgehäuse bereitgestellt. Das Chipgehäuse kann einen Chip, eine Metallkontaktstruktur, die ein Nicht-Edelmetall aufweist und den Chip elektrisch kontaktiert, ein Packagingmaterial und eine Schutzschicht, die einen Abschnitt, der an einer Schnittstelle zwischen einem Abschnitt der Metallkontaktstruktur und dem Packagingmaterial gebildet ist, aufweist oder im Wesentlichen aus ihm besteht, aufweisen, wobei die Schutzschicht ein Edelmetall aufweisen kann, wobei der Abschnitt der Schutzschicht eine Mehrzahl von Bereichen aufweisen kann, die frei von dem Edelmetall sind, und wobei die Bereiche, die frei von dem Edelmetall sind, eine Schnittstelle zwischen dem Packagingmaterial und dem Nicht-Edelmetall der Metallkontaktstruktur bereitstellen können.

公开(公告)号：DE10014659A1

公开(公告)日：2001-10-11

申请号：DE10014659

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VIETZKE DIRK ,  STECHER MATTHIAS ,  SCHULZE HANS-JOACHIM ,  PERI HERMANN ,  NELLE PETER ,  PLOSS REINHARD ,  KANERT WERNER

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/32 ,  H01L29/78 ,  H01L27/08 ,  H01L29/04 ,  H01L29/06

Abstract: The semiconducting circuit arrangement has a substrate (10) of a first conductor type (p) and a component region (20) on the front side of the substrate with a number of insulated troughs (25,26,28) of a second conductor type (n). At least one power component in the component region has a load connection (25) of the second conductor type for connecting a load. The substrate has a recombination zone (RZ) for the recombination of minority carriers injected into the substrate from the load connection.

公开(公告)号：DE10005774A1

公开(公告)日：2001-08-23

申请号：DE10005774

申请日：2000-02-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WERNER WOLFGANG ,  SOMMER PETER ,  KANERT WERNER

IPC: H01L29/78 ,  H01L29/872

Abstract: DMOS cell consists of DMOS transistor (11) and Schottky diode (12) which lie parallel to the source-drain path of the transistor. The source zone (6) of the transistor is in contact with a source-contact layer (7, 14) via a contact hole (8) in a gate insulating layer (9). The Schottky diode is formed in the contact hole between the source-contact layer and the drain zone (1, 2) of the transistor. Preferred Features: The source-contact layer is provided with a Schottky metallization (13) made from tungsten silicide, tantalum silicide, platinum silicide or molybdenum silicide, and has a plug (14) made from conducting polycrystalline silicon.

公开(公告)号：DE19954600C1

公开(公告)日：2000-11-16

申请号：DE19954600

申请日：1999-11-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HERMANN ,  PFIRSCH FRANK ,  KANERT WERNER

IPC: H01L27/06 ,  H01L23/58 ,  F02N11/08 ,  F02P3/04 ,  H01L27/08 ,  H01L29/06 ,  H01L29/739 ,  H01L29/866

Abstract: The IC has a peripheral edge with aluminium or polysilicon rings, a transition from the edge to the Zener diodes and an edge termination in which the Zener diodes are integrated, whereby the Zener diodes have voltage tappings that are not arranged at equal intervals. The distance of the individual rings from the Zener diodes is larger. Aluminium field plates can be arranged over polysilicon rings (SR1-SR5) above an insulating layer and connected to the potential of the rings via contact holes.