11.
    发明专利
    未知

    公开(公告)号:DE50208719D1

    公开(公告)日:2006-12-28

    申请号:DE50208719

    申请日:2002-07-02

    Abstract: The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method comprises generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure comprises an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which comprises a conductive layer and a mask layer on the conductive layer. The mask layer is thinned in the area of the gate electrode. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed.

    12.
    发明专利
    未知

    公开(公告)号:DE50110697D1

    公开(公告)日:2006-09-21

    申请号:DE50110697

    申请日:2001-01-08

    Abstract: A silicon-germanium bipolar transistor includes a silicon substrate in which a first n-doped emitter region, a second p-doped base region adjoining the latter and a third n-doped collector region adjoining the latter, are formed. A first space charge zone is formed between the emitter region and the base region and a second space charge zone is formed between the base region and the collector region. The base region and an edge zone of the adjoining emitter region are alloyed with germanium. The germanium concentration in the emitter region rises toward the base region. The germanium concentration in a junction region containing the first space charge zone rises less sharply than in the emitter region or decreases and, in the base region, it initially again rises more sharply than in the junction region.

    13.
    发明专利
    未知

    公开(公告)号:AT336079T

    公开(公告)日:2006-09-15

    申请号:AT01905609

    申请日:2001-01-08

    Abstract: A silicon-germanium bipolar transistor includes a silicon substrate in which a first n-doped emitter region, a second p-doped base region adjoining the latter and a third n-doped collector region adjoining the latter, are formed. A first space charge zone is formed between the emitter region and the base region and a second space charge zone is formed between the base region and the collector region. The base region and an edge zone of the adjoining emitter region are alloyed with germanium. The germanium concentration in the emitter region rises toward the base region. The germanium concentration in a junction region containing the first space charge zone rises less sharply than in the emitter region or decreases and, in the base region, it initially again rises more sharply than in the junction region.

    14.
    发明专利
    未知

    公开(公告)号:DE10002364A1

    公开(公告)日:2001-08-02

    申请号:DE10002364

    申请日:2000-01-20

    Abstract: The invention relates to a silicon/germanium bipolar transistor, wherein a first n doped emitter region (1) and a second subsequent p doped base region and a third subsequent n doped collector region are formed in a silicon substrate (7). A first space charge region (4) is formed between the emitter region (1) and the base region (2). A second space charge region (5) is formed between the base region (2) and a collector region (3). The base region (2) and the edge region of the bordering emitter region (1) is alloyed with germanium. The concentration of germanium increases in the emitter region (1) leading towards the base region (2). The concentration of germanium in a transition area in which the first space charge zone (4) is located increases to a lesser degree than in the emitter region (1) or even decreases. The concentration of germanium in the base region (2) increases to a greater degree than in the transition region.

    15.
    发明专利
    未知

    公开(公告)号:DE19958062A1

    公开(公告)日:2001-07-05

    申请号:DE19958062

    申请日:1999-12-02

    Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.

    System und Verfahren für ein Mikrofon

    公开(公告)号:DE102015108918A1

    公开(公告)日:2015-12-10

    申请号:DE102015108918

    申请日:2015-06-05

    Abstract: Nach einer Ausführungsform aufweist eine mikrohergestellte Struktur (100) einen Hohlraum (109), der in einem Substrat (108) angeordnet ist, eine erste Klemmschicht (104), die über dem Substrat (108) liegt, eine auslenkbare Membran (102), die über der ersten Klemmschicht (104) liegt, und eine zweite Klemmschicht (106), die über der auslenkbaren Membran (102) liegt. Ein Abschnitt der zweiten Klemmschicht (106) überlappt den Hohlraum (109).

    18.
    发明专利
    未知

    公开(公告)号:DE10306597B4

    公开(公告)日:2005-11-17

    申请号:DE10306597

    申请日:2003-02-17

    Abstract: A pn junction is formed between a semiconductor zone (113) and a semiconductor layer (111). Under the zone a buried semiconductor layer (101) is formed in which a recess (103) is provided containing a further semiconductor area (105) lower in he substrate than the buried layer and of the same doping type as the semiconductor layer. An independent claim is also included for a method of manufacture.

    19.
    发明专利
    未知

    公开(公告)号:DE10337569A1

    公开(公告)日:2005-03-24

    申请号:DE10337569

    申请日:2003-08-14

    Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.

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