公开(公告)号：DE10244569B4

公开(公告)日：2006-08-10

申请号：DE10244569

申请日：2002-09-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT ,  WEYBRIGHT MARY

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51

Abstract: Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an active device area capped with a pad oxide layer bounded by one or more isolation trenches, providing a sacrificial oxide layer by thickening said pad oxide layer to a desired oxide thickness, in using said thickened pad oxide layer as said sacrificial oxide layer for device implantation, stripping said sacrificial pad oxide layer after use, and capping said semiconductor gate with a final gate oxide layer.

公开(公告)号：DE102004004594A1

公开(公告)日：2004-09-09

申请号：DE102004004594

申请日：2004-01-29

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MALIK RAJEEV ,  RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  GLUSCHENKOV OLEG ,  YAN HONGWEN ,  YANG HAINING

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal layers comprising a gate metalis provided. The gate metal is recessed away from the gate stack sidewall using a chemical etch. The gate metal of the gate stack structure is selectively oxidized to form a metal oxide that at least partly fills the recess.

公开(公告)号：DE10305729A1

公开(公告)日：2003-08-28

申请号：DE10305729

申请日：2003-02-12

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHAKRAVARTI ASHIMA B ,  GLUSCHENKOV OLEG ,  MCSTAY IRENE

IPC: C23C16/04 ,  C23C16/44 ,  C23C16/455 ,  C23C16/48 ,  C23C16/52 ,  H01L21/00 ,  H01L21/316 ,  H01L21/318 ,  H01L21/8242 ,  H01L21/3205 ,  H01L21/324

Abstract: An apparatus (110) and method for depositing material on a semiconductor wafer with non-planar structures (114). The wafer (114) is positioned in a chamber (111), and reactive gases (132) are introduced into the chamber (111). The gases (132) and wafer (114) are heated, wherein the gas (132) temperature in the process chamber (111) and in the vicinity of the wafer (114) surface is lower than the temperature of the wafer (114) surface. A material is deposited on the wafer (114) surface using chemical vapor deposition. A gas cooler may be utilized to lower the temperature of the reactive gases (132) while the wafer (114) is heated.

公开(公告)号：DE10341576B4

公开(公告)日：2007-04-19

申请号：DE10341576

申请日：2003-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AKATSU HIROYUKI ,  GLUSCHENKOV OLEG ,  PARKINSON PORSHIA SHANE ,  RAMACHANDRAN RAVIKUMAR ,  SETTLEMYER KENNETH T ,  TEWS HELMUT

IPC: H01L21/8242 ,  H01L21/20

Abstract: Microelectronic structure is manufactured by: (i) forming set of openings in surface of substrate (10); (ii) forming film stack having layers on each sidewall of openings; (iii) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (iv) thermally nitriding silicon layer on upper portion of structure. Fabrication of microelectronic structure comprises: (a) forming set of openings in surface of substrate; (b) forming film stack having layers on each sidewall of openings; (c) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (d) thermally nitriding silicon layer on upper portion of structure to form nitrided silicon layer having first thickness limited through reaction kinetics and less than barrier thickness. The openings have sidewalls that extend to a common bottom wall. The layers include nitride diffusion barrier layer having a barrier thickness and silicon layer deposited after the barrier layer.

公开(公告)号：AU2003273328A1

公开(公告)日：2004-04-08

申请号：AU2003273328

申请日：2003-09-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE ,  SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78

Abstract: A conductive structure in an integrated circuit ( 12 ), and a method of forming the structure, is provided that includes a polysilicon layer ( 30 ), a thin layer containing titanium over the polysilicon, a tungsten nitride layer ( 34 ) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region ( 38 ) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer ( 30 ) and the tungsten layer ( 32 ), and provides low interface resistance between the tungsten layer and the polysilicon layer.

公开(公告)号：DE10341576A1

公开(公告)日：2004-03-18

申请号：DE10341576

申请日：2003-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AKATSU HIROYUKI ,  GLUSCHENKOV OLEG ,  PARKINSON PORSHIA SHANE ,  RAMACHANDRAN RAVIKUMAR ,  SETTLEMYER KENNETH T ,  TEWS HELMUT

IPC: H01L21/20 ,  H01L21/8242

Abstract: Microelectronic structure is manufactured by: (i) forming set of openings in surface of substrate (10); (ii) forming film stack having layers on each sidewall of openings; (iii) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (iv) thermally nitriding silicon layer on upper portion of structure. Fabrication of microelectronic structure comprises: (a) forming set of openings in surface of substrate; (b) forming film stack having layers on each sidewall of openings; (c) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (d) thermally nitriding silicon layer on upper portion of structure to form nitrided silicon layer having first thickness limited through reaction kinetics and less than barrier thickness. The openings have sidewalls that extend to a common bottom wall. The layers include nitride diffusion barrier layer having a barrier thickness and silicon layer deposited after the barrier layer.

公开(公告)号：EP1927128A4

公开(公告)日：2009-01-28

申请号：EP06804017

申请日：2006-09-22

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC classification number: H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

Abstract: The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i-e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, and the first gate oxide is higher k than the second gate oxide or vice-versa.

公开(公告)号：EP1382064A4

公开(公告)日：2008-05-07

申请号：EP01987463

申请日：2001-12-27

Applicant: IBM

Inventor： DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  HEDGE SURYANARAYAN G ,  KAPLAN RICHARD ,  KHARE MUKESH

IPC: H01L21/3205 ,  H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/31 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/4941

Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, C1, He, Ar, Kr, and Xe; and mixtures thereof.

公开(公告)号：EP2108192A4

公开(公告)日：2009-12-30

申请号：EP07855285

申请日：2007-12-20

Applicant: IBM

Inventor： LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

IPC: H01L27/10 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

公开(公告)号：EP1683187A4

公开(公告)日：2008-08-27

申请号：EP04810633

申请日：2004-11-09

Applicant: IBM

Inventor： DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.