公开(公告)号：DE602004025966D1

公开(公告)日：2010-04-22

申请号：DE602004025966

申请日：2004-11-29

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  DETAVERNIER CHRISTOPHER ,  JAMMY RAJARAO ,  SAENGER KATHERINE L

IPC: C22C32/00 ,  C23C14/06 ,  C23C16/32 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/49

Abstract: A semiconductor device such as a complementary metal oxide semiconductor (CMOS) including at least one FET that includes a gate electrode including a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

公开(公告)号：AU2003263367A1

公开(公告)日：2004-04-08

申请号：AU2003263367

申请日：2003-09-15

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE ALFRED ,  HSU LOUIS LU-CHEN ,  SHEPARD JOSEPH FRANCIS JR ,  WONG KWONG HON

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423

公开(公告)号：WO2007112361A3

公开(公告)日：2008-04-10

申请号：PCT/US2007064946

申请日：2007-03-26

Applicant: IBM ,  CABRAL CYRIL JR ,  DELIGIANNI HARIKLIA ,  KNARR RANDOLPH F ,  MALHOTRA SANDRA G ,  ROSSNAGEL STEPHEN ,  SHAO XIAOYAN ,  TOPOL ANNA ,  VEREECKEN PHILIPPE M

Inventor： CABRAL CYRIL JR ,  DELIGIANNI HARIKLIA ,  KNARR RANDOLPH F ,  MALHOTRA SANDRA G ,  ROSSNAGEL STEPHEN ,  SHAO XIAOYAN ,  TOPOL ANNA ,  VEREECKEN PHILIPPE M

IPC: H01L29/02

CPC classification number: H01L23/485 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a suicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the suicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.

Abstract translation: 一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的自杀或锗化物层，例如钴和/或镍; 接触层包括位于介电层顶部并且在空腔内并且与底部上的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。 金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。 当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。 当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

公开(公告)号：WO2006055226A3

公开(公告)日：2007-08-23

申请号：PCT/US2005039288

申请日：2005-11-01

Applicant: IBM ,  BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

Abstract translation: 提供了一种半导体结构，其包括在栅极电介质和栅电极之间的V 1稳定层。 VST稳定层能够将结构的阈值电压和平带电压稳定到目标值，并且包括氮化金属氧化物或无氮金属氧化物，其条件是当V < 稳定层包括无氮金属氧化物，半导体衬底或栅极电介质中的至少一个包括氮。 本发明还提供一种制造这种结构的方法。

公开(公告)号：WO2005062752A2

公开(公告)日：2005-07-14

申请号：PCT/US2004039855

申请日：2004-11-29

Applicant: IBM ,  CABRAL CYRIL JR ,  DETAVERNIER CHRISTOPHER ,  JAMMY RAJARAO ,  SAENGER KATHERINE L

Inventor： CABRAL CYRIL JR ,  DETAVERNIER CHRISTOPHER ,  JAMMY RAJARAO ,  SAENGER KATHERINE L

IPC: H01L21/8238 ,  H01L27/108 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/823842

Abstract: A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

Abstract translation: 提供了包括至少一个FET的半导体器件，例如互补金属氧化物半导体（CMOS），其包括包含金属碳化物的栅电极和制造方法。 CMOS包括双功能金属栅电极，由此双功能功能由金属和金属的碳化物提供。

公开(公告)号：GB2508749A

公开(公告)日：2014-06-11

申请号：GB201403444

申请日：2012-07-18

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  NOGAMI TAKESHI ,  GAMBINO JEFFREY P ,  HUANG QIANG ,  RODBELL KENNETH P

IPC: H01L21/768 ,  H01L21/288 ,  H01L23/532

Abstract: A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90nm technologies. Preferably, bamboo grains are separated at distances less than the "Blech" length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.

公开(公告)号：AT438928T

公开(公告)日：2009-08-15

申请号：AT04786558

申请日：2004-08-20

Applicant: IBM

Inventor： STEEGEN AN ,  KU VICTOR ,  WONG KWONG ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL JR ,  JAMISON PAUL

IPC: H01L29/94 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

公开(公告)号：GB2508749B

公开(公告)日：2015-12-02

申请号：GB201403444

申请日：2012-07-18

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  NOGAMI TAKESHI ,  GAMBINO JEFFREY P ,  HUANG QIANG ,  RODBELL KENNETH P

IPC: H01L21/768 ,  H01L21/288 ,  H01L23/532

Abstract: A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.

公开(公告)号：DE602004026753D1

公开(公告)日：2010-06-02

申请号：DE602004026753

申请日：2004-09-08

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  IEONG MEIKEI ,  KEDZIERSKI JAKUB

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/336

Abstract: A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation, the polysilicon is amorphized. In a further embodiment, siliciding is performed at a low substrate temperature.

公开(公告)号：AU2002357054A1

公开(公告)日：2003-06-10

申请号：AU2002357054

申请日：2002-11-27

Applicant: IBM

Inventor： KIM HYUNGJUN ,  MCFEELY FENTON ,  NARAYANAN VIJAY ,  RODBELL KENNETH ,  YURKAS JOHN ,  AMOS RICKY ,  BUCHANAN DOUGLAS ,  CABRAL CYRIL JR ,  CALLEGARI ALESSANDRO ,  GUHA SUPRATIK

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/30 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76

Abstract: A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.