公开(公告)号：DE602004022435D1

公开(公告)日：2009-09-17

申请号：DE602004022435

申请日：2004-08-20

Applicant: IBM

Inventor： STEEGEN AN L ,  KU VICTOR ,  WONG KWONG HON ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL OSSINING ,  JAMISON PAUL

IPC: H01L29/94 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

公开(公告)号：AU2003263367A1

公开(公告)日：2004-04-08

申请号：AU2003263367

申请日：2003-09-15

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE ALFRED ,  HSU LOUIS LU-CHEN ,  SHEPARD JOSEPH FRANCIS JR ,  WONG KWONG HON

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423

公开(公告)号：DE10243468A1

公开(公告)日：2003-05-15

申请号：DE10243468

申请日：2002-09-19

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： LIAN JINGYU ,  LIN CHENTING ,  SAENGER KATHERINE ,  WONG KWONG HON

IPC: C23C16/40 ,  C23C16/56 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3105 ,  H01L21/8239

Abstract: A method for forming a crystalline dielectric layer deposits an amorphous metallic oxide dielectric layer on a surface. The amorphous metallic oxide dielectric layer is treated with a plasma at a temperature of less than or equal to 400 degrees Celsius to form a crystalline layer.

公开(公告)号：GB2409932A

公开(公告)日：2005-07-13

申请号：GB0427899

申请日：2004-12-21

Applicant: IBM

Inventor： KU VICTOR ,  STEEGEN AN ,  WANN HSING-JEN ,  WONG KWONG HON

IPC: H01L21/335 ,  H01L21/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: A method is provided for fabricating a gate structure for a semiconductor device in which the gate structure has an inner spacer. A replacement-gate process is used in which material is removed in a gate region to expose a portion of the substrate; a gate dielectric is formed on the exposed portion of the substrate; and an inner spacer layer is formed overlying the gate dielectric and the dielectric material. A silicon layer is then formed which overlies the inner spacer layer. The structure is then planarized so that portions of the silicon layer and inner spacer layer remain in the gate region. A silicide gate structure is then formed from the silicon; the silicide gate structure is separated from dielectric material surrounding the gate by the inner spacer layer. The semiconductor device may include a first gate region and a second gate region with an interface therebetween, with the inner spacer layer covering the interface. When the device has two gate regions, the process may be used in both gate regions, so as to produce separate silicide structures, with an inner spacer separating the two structures.

公开(公告)号：DE102004016963A1

公开(公告)日：2004-11-18

申请号：DE102004016963

申请日：2004-04-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： WISE MICHAEL ,  LIMB YOUNG ,  WONG KWONG HON ,  LIAN JENNY ,  NAGEL NICOLAS

IPC: B32B9/04 ,  B32B15/04 ,  H01L21/02 ,  H01L21/8239 ,  H01L21/8242

Abstract: Si, Al, Al plus TiN, and IrO2 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (SiO 2 ) substrate in capacitor structures of memory devices.

公开(公告)号：DE102004004790A1

公开(公告)日：2004-09-09

申请号：DE102004004790

申请日：2004-01-30

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： SHAFER PADRAIC ,  IGGULDEN ROY C ,  WONG KWONG HON ,  ROBL WERNER

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/49 ,  H01L21/336 ,  H01L21/8246

公开(公告)号：AU9209001A

公开(公告)日：2002-04-22

申请号：AU9209001

申请日：2001-10-05

Applicant: IBM

Inventor： CLEVENGER LAWRENCE ,  HSU LOUIS LU-CHEN ,  WONG KWONG HON

IPC: H01L21/02 ,  H01L27/06

Abstract: An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

公开(公告)号：AU1330897A

公开(公告)日：1998-07-15

申请号：AU1330897

申请日：1996-12-16

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  DELIGIANNI HARIKLIA ,  DUKOVIC JOHN OWEN ,  HORKANS WILMA JEAN ,  UZOH CYPRIAN EMEKA ,  WONG KWONG HON ,  HU CHAO-KUN ,  EDELSTEIN DANIEL CHARLES ,  RODBELL KENNETH PARKER ,  HURD JEFFERY LOUIS

IPC: C25D7/12 ,  H01L21/28 ,  H01L21/288 ,  H01L21/768 ,  H01L23/532

Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches.