公开(公告)号：DE50214199D1

公开(公告)日：2010-03-25

申请号：DE50214199

申请日：2002-02-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANOSCH MARTIN ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  STENGL REINHARD

IPC: H01L29/737 ,  H01L21/331

公开(公告)号：DE59914245D1

公开(公告)日：2007-04-19

申请号：DE59914245

申请日：1999-05-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  LEHMANN VOLKER ,  STENGL REINHARD ,  WENDT HERMANN ,  LANGE GERRIT ,  BACHHOFER HARALD ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT

IPC: H01L21/8242 ,  H01L27/108

Abstract: A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

公开(公告)号：DE19958151B4

公开(公告)日：2006-05-04

申请号：DE19958151

申请日：1999-12-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NELLE PETER ,  FISCHER HERMANN ,  WERNER WOLFGANG ,  SCHAEFER HERBERT

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/06

Abstract: Lateral high voltage semiconductor element comprises a semiconductor substrate (1) of first conductivity with a semiconductor layer (2) of second conductivity having an active zone (3). Semiconductor regions (11, 12) of first and second conductivity are provided on the semiconductor layer by selective multiple epitaxy. An Independent claim is also included for a process for the production of a lateral high voltage semiconductor element, comprising back-etching an insulating layer provided on the edges of the semiconductor regions (11, 12) after selective multiple epitaxy and then carrying out further selective epitaxy to form a connecting layer. Preferred Features: The semiconductor regions have a thickness of 1-100 nm, especially 50 nm.

公开(公告)号：DE19953333B4

公开(公告)日：2004-07-15

申请号：DE19953333

申请日：1999-11-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NELLE PETER ,  SCHAEFER HERBERT ,  VIETZKE DIRK ,  STECHER MATTHIAS ,  BAUMGARTL JOHANNES ,  PERI HERMANN

IPC: H01L21/74 ,  H01L21/761 ,  H01L29/06

公开(公告)号：DE59705585D1

公开(公告)日：2002-01-10

申请号：DE59705585

申请日：1997-09-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUSTIG BERNHARD ,  SCHAEFER HERBERT ,  FRANOSCH MARTIN

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

Abstract: PCT No. PCT/DE97/01933 Sec. 371 Date Jun. 4, 1999 Sec. 102(e) Date Jun. 4, 1999 PCT Filed Sep. 3, 1996 PCT Pub. No. WO98/13865 PCT Pub. Date Apr. 2, 1998In order to produce a MOS transistor with HDD profile and LDD profile, the HDD profile is firstly formed, followed by the LDD profile, in the area for the LDD profile in order to produce steep dopant profiles. The LDD profile is preferably produced by etching and in situ doped selective epitaxy.

公开(公告)号：DE59705303D1

公开(公告)日：2001-12-13

申请号：DE59705303

申请日：1997-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER HERBERT ,  FRANOSCH MARTIN ,  STENGL REINHARD ,  LEHMANN VOLKER ,  REISINGER HANS ,  WENDT HERMANN

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3205

Abstract: PCT No. PCT/DE97/01408 Sec. 371 Date Feb. 9, 1999 Sec. 102(e) Date Feb. 9, 1999 PCT Filed Jul. 3, 1997 PCT Pub. No. WO98/07184 PCT Pub. Date Feb. 19, 1998For manufacturing a capacitor that is essentially suited for DRAM arrangements, column structures that form an electrode of the capacitor are etched upon employment of a statistical mask that is produced without lithographic steps by nucleus formation of Si/Ge and subsequent selective epitaxy. Structure sizes below 100 nm can be realized in the statistical mask. Surface enlargement factors up to 60 are thus achieved.

公开(公告)号：DE10023872C1

公开(公告)日：2001-12-13

申请号：DE10023872

申请日：2000-05-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MARKSTEINER STEPHAN ,  AIGNER ROBERT ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT

IPC: B81C1/00

Abstract: Producing microstructures layers comprises applying a layer (3) to be perforated on a sacrificial layer (2) applied on a substrate (1); depositing crystals (6) on the layer to be perforated and forming a mask layer which covers the regions left free by the crystals; producing perforations while the layer is removed from the mask and removing the sacrificial layer using perforations as etching openings. Preferred Features: The crystals are made from silicon. In the second step, a layer of material for the mask layer is deposited on the crystals and between the crystals, leveled and the crystals removed so that the leveled layer remains as the mask layer.

公开(公告)号：AT508475T

公开(公告)日：2011-05-15

申请号：AT01927654

申请日：2001-02-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  MEISTER THOMAS ,  STENGL REINHARD

IPC: H01L29/732 ,  H01L21/331

公开(公告)号：DE102006046727B4

公开(公告)日：2010-02-18

申请号：DE102006046727

申请日：2006-10-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MEISTER THOMAS ,  SCHAEFER HERBERT ,  BOECK JOSEF ,  LACHNER RUDOLF

IPC: H01L21/8222 ,  H01L21/331 ,  H01L27/06 ,  H01L29/737 ,  H01L29/93

公开(公告)号：SG155055A1

公开(公告)日：2009-09-30

申请号：SG2007029515

申请日：2003-10-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOECK JOSEF ,  LACHNER RUDOLF ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  SECK MARTIN ,  STENGL REINHARD

IPC: H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/08

Abstract: Method for producing transistor structure The invention relates to a method for fabricating a transistor structure, comprising at least a first and a second bipolar transistor having different collector widths. The invention is distinguished by the fact that all junctions between differently doped regions have a sharp interface. In this case, by way of example, a first collector region 2.1 is suitable for a high- frequency transistor with high limiting frequencies fT and a second collector region 2.2 is suitable for a high-voltage transistor with increased breakdown voltages. Figure 3c