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    31.
    发明专利
    未知

    公开(公告)号：DE10334946A1

    公开(公告)日：2004-03-18

    申请号：DE10334946

    申请日：2003-07-31

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： BEINTNER JOCHEN ,  CHUDZIK MICHAEL PATRICK ,  RAJARAO JAMMY ,  DIVAKARUNI RAMACHANDRA

    IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

    Abstract: In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.

    32.
    发明专利
    未知

    公开(公告)号：DE10226569A1

    公开(公告)日：2003-01-16

    申请号：DE10226569

    申请日：2002-06-14

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： DIVAKARUNI RAMACHANDRA ,  DEV PRAKASH ,  MALIK RAJEEV ,  NESBIT LARRY

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.

    33.
    发明专利
    未知

    公开(公告)号：DE60133214D1

    公开(公告)日：2008-04-24

    申请号：DE60133214

    申请日：2001-11-13

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HOH PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

    IPC: H01L21/8242 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8239

    Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

    STRUCTURES AND METHODS OF ANTI-FUSE FORMATION IN SOI
    34.
    发明专利
    STRUCTURES AND METHODS OF ANTI-FUSE FORMATION IN SOI 未知

    公开(公告)号：MY134452A

    公开(公告)日：2007-12-31

    申请号：MYPI20054051

    申请日：2001-05-23

    Applicant: IBM

    Inventor： BERTIN CLAUDE L ,  DIVAKARUNI RAMACHANDRA ,  HOUGHTON RUSSELL J ,  MANDELMAN JACK A ,  TONTI WILLIAM R

    IPC: H01L21/336 ,  H01L21/82 ,  H01L21/00 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12

    Abstract: AN ANTI-FUSE STRUCTURE THAT CAN BE PROGRAMMED AT LOW VOLTAGE AND CURRENT AND WHICH POTENTIALLY CONSUMES VERY LITTLE CHIP SPACES AND CAN BE FORMED INTERSTITIALLY BETWEEN ELEMENTS SPACED BY A MINIMUM LITHOGRAPHIC FEATURE SIZE IS FORMED ON A COMPOSITE SUBSTRATE SUCH AS A SILICON-ONINSULATOR WAFER BY ETCHING A CONTACT THROUGH AN INSULATOR TO A SUPPORT SEMICONDUCTOR LAYER, PREFERABLY IN COMBINATION WITH FORMATION OF A CAPACITOR-LIKE STRUCTURE REACHING TO OR INTO THE SUPPORT LAYER. THE ANTI-FUSE MAY BE PROGRAMMED EITHER BY THE SELECTED LOCATION OF CONDUCTOR FORMATION AND/OR DAMAGING A DIELECTRIC OF THE CAPACITOR-LIKE STRUCTURE. AN INSULATING COLLAR (38, 90) IS USED TO SURROUND A PORTION OF EITHER THE CONDUCTOR (42, 100) OR THE CAPACITOR-LIKE STRUCTURE TO CONFINE DAMAGE TO THE DESIRED LOCATION.HEATING EFFECTS VOLTAGE AND NOISE DUE TO PROGRAMMING CURRENTS ARE EFFECTIVELY ISOLATED TO THE BULK SILICON LAYER, PERMITTING PROGRAMMING DURING NORMAL OPERATION OF THE DEVICE. THUS THE POTENTIAL FOR SELF-REPAIR WITHOUT INTERRUPTION OF OPERATION IS REALIZED.(FIG 6)

    35.
    发明专利
    未知

    公开(公告)号：DE10344862B4

    公开(公告)日：2007-12-20

    申请号：DE10344862

    申请日：2003-09-26

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

    IPC: H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

    Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

    36.
    发明专利
    未知

    公开(公告)号：DE10324491A1

    公开(公告)日：2004-01-08

    申请号：DE10324491

    申请日：2003-05-30

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： DIVAKARUNI RAMACHANDRA ,  MALIK RAIEEV ,  RENGARAJAN RAIESH

    IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    Abstract: Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56 cover the dram array 12 and a gate oxide layer 42 and an undoped polysilicon layer 44 cover the support area 14. A common mask is applied and patterned over the substrate to define the wordlines line structures in the dram array 12 and the gate structures in the support 14. The unwanted portions of the layers 54, 56, 42 and 44 are removed by etching.

    Source-drain extension formation in replacement metal gate transistor device
    38.
    发明专利
    Source-drain extension formation in replacement metal gate transistor device 未知

    公开(公告)号：GB2497849A

    公开(公告)日：2013-06-26

    申请号：GB201222136

    申请日：2012-12-10

    Applicant: IBM

    Inventor： YAMASHITA TENKO ,  DIVAKARUNI RAMACHANDRA ,  BU HUIMING ,  SHANG HUILING ,  CHUNG-HSUN LIN ,  ANDO TAKASHI ,  DORIS BRUCE B

    IPC: H01L29/66 ,  H01L29/78

    Abstract: A method to fabricate a field effect transistor includes forming on a surface of a semiconductor 10 a dummy gate structure comprised of a plug 14, forming a first spacer 18 surrounding the plug, the first spacer being a sacrificial spacer, and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor adjacent to an outer sidewall of the first spacer to form source and drain extension regions 20, such that the implanted species extends under the outer sidewall of the first spacer by an amount that is a function of the angle of the ion implant. The method further includes performing a laser anneal to activate the source and drain extension implants. In further processing, a second spacer is formed surrounding the first spacer, the first spacer and dummy gate are removed to form an opening and a gate stack is deposited in the opening.

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