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    TRANSISTOR DE NANOFOLHAS COM PILHA DE PORTA ASSIMÉTRICA
    31.
    发明专利
    TRANSISTOR DE NANOFOLHAS COM PILHA DE PORTA ASSIMÉTRICA 未知

    公开(公告)号：BR112022021777A2

    公开(公告)日：2022-12-13

    申请号：BR112022021777

    申请日：2021-04-30

    Applicant: IBM

    Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG-SHENG KANG

    IPC: H01L29/78 ,  H01L21/336

    Abstract: TRANSISTOR DE NANOFOLHAS COM PILHA DE PORTA ASSIMÉTRICA. Métodos e estruturas resultantes para dispositivos de nanofolhas com pilhas de portas assimétricas são descritos. Uma pilha de nanofolhas (102) é formada sobre um substrato (104). A pilha de nanofolhas (102) inclui camadas semicondutoras alternadas (108) e camadas de sacrifício (110). Um revestimento de sacrifício (202) é formado sobre a pilha de nanofolhas (102) e uma estrutura de porta dielétrica (204) é formada sobre a pilha de nanofolhas (102) e o revestimento de sacrifício (202). Um primeiro espaçador interno (302) é formado em uma parede lateral das camadas de sacrifício (110). Uma porta (112) é formada sobre regiões de canal da pilha de nanofolhas (102). A porta (112) inclui uma ponte condutora que se estende sobre o substrato (104) em uma direção ortogonal à pilha de nanofolhas (102). Um segundo espaçador interno (902) é formado em uma parede lateral do portão (112). O primeiro espaçador interno (302) é formado antes da pilha de portas (112), enquanto o segundo espaçador interno (902) é formado depois e, consequentemente, a pilha de portas (112) é assimétrica.

    Fabrication of logic devices and power devices on the same substrate
    32.
    发明专利
    Fabrication of logic devices and power devices on the same substrate 未知

    公开(公告)号：GB2582087B

    公开(公告)日：2022-03-30

    申请号：GB202007421

    申请日：2018-12-03

    Applicant: IBM

    Inventor： JUNTAO LI ,  KANGGUO CHENG ,  LIYING JLANG ,  JOHN GERARD GAUDIELLO

    IPC: H01L21/84

    Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.

    Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions
    33.
    发明专利
    Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions 未知

    公开(公告)号：GB2595125A

    公开(公告)日：2021-11-17

    申请号：GB202111358

    申请日：2020-02-24

    Applicant: IBM

    Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS JEAN LOUBET

    IPC: H01L29/41

    Abstract: Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET)architecture that includes a center fin region and one or more vertically stacked nanosheets.In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate.The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers.A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers.The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers.The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.

    Super long channel device within VFET architecture
    34.
    发明专利
    Super long channel device within VFET architecture 未知

    公开(公告)号：GB2577417B

    公开(公告)日：2021-09-08

    申请号：GB201917399

    申请日：2018-05-10

    Applicant: IBM

    Inventor： MARC BERGENDAHL ,  ERIC MILLER ,  FEE LI LIE ,  SEAN TEEHAN ,  KANGGUO CHENG ,  JOHN RYAN SPORRE ,  GAURI KARVE

    IPC: H01L27/04

    Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

    Vertical FET with reduced parasitic capacitance
    35.
    发明专利
    Vertical FET with reduced parasitic capacitance 未知

    公开(公告)号：GB2577185B

    公开(公告)日：2020-11-04

    申请号：GB201915887

    申请日：2018-04-11

    Applicant: IBM

    Inventor： XIN MIAO ,  KANGGUO CHENG ,  CHEN ZHANG ,  WENYU XU ,  PHILIP JOSEPH OLDIGES

    IPC: H01L29/78 ,  H01L29/66

    Abstract: A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.

    H-shaped VFET with increased current drivability
    36.
    发明专利
    H-shaped VFET with increased current drivability 未知

    公开(公告)号：GB2581893A

    公开(公告)日：2020-09-02

    申请号：GB202006464

    申请日：2018-11-01

    Applicant: IBM

    Inventor： CHEN ZHANG ,  KANGGUO CHENG ,  TENKO YAMASHITA ,  XIN MIAO ,  WENYU XU

    IPC: H01L29/78

    Abstract: Techniques for increasing Weff VFET devices are provided. In one aspect, a method of forming a fin structure includes: depositing a hardmask onto a substrate; depositing a mandrel material onto the hardmask; patterning the mandrel material along a first direction to form first mandrels; forming first spacers alongside the first mandrels; forming second mandrels in between the first mandrels; pattering the first/second mandrels along a second direction perpendicular to the first direction; forming second spacers, perpendicular to the first spacers, alongside the first/second mandrels; selectively removing the first/second mandrels leaving behind a ladder-shaped pattern formed by the first/second spacers; transferring the ladder-shaped pattern to the hardmask and then to the substrate. A method of forming a VFET device, a VFET fin structure, and a VFET device are also provided.

    Vertical FET with reduced parasitic capacitance
    37.
    发明专利
    Vertical FET with reduced parasitic capacitance 未知

    公开(公告)号：GB2577185A

    公开(公告)日：2020-03-18

    申请号：GB201915887

    申请日：2018-04-11

    Applicant: IBM

    Inventor： XIN MIAO ,  KANGGUO CHENG ,  CHEN ZHANG ,  WENYU XU ,  PHILIP JOSEPH OLDIGES

    IPC: H01L29/78 ,  H01L29/66

    Abstract: A method for reducing parasitic capacitance of a semiconductor structure includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.

    Air gap spacer formation for nano-scale semiconductor devices
    39.
    发明专利
    Air gap spacer formation for nano-scale semiconductor devices 未知

    公开(公告)号：GB2567363A

    公开(公告)日：2019-04-10

    申请号：GB201901614

    申请日：2017-07-21

    Applicant: IBM

    Inventor： SON VAN NGUYEN ,  TENKO YAMASHITA ,  KANGGUO CHENG ,  THOMAS JASPER HAIGH JR ,  CHANRO PARK ,  ERIC LINIGER ,  JUNTAO LI ,  SANJAY MEHTA

    IPC: H01L21/768 ,  H01L21/02 ,  H01L29/49

    Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

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